A new tuning scheme for linearly tunable high-Q filters is proposed. The tuning method is based on using the phase information for both frequency and Q factor tuning. There is no need to find out the relationship between a filter's passband magnitude and Q. A gm-C biquadratic filter is designed to demonstrate the proposed tuning circuitry. The project includes a phase locked loop (PLL) based frequency tuning loop, reference clock generator, and differential difference amplifier (DDA) for dealing with frequency and Q factor tuning loop and linearly tunable second order gm-C bandpass filter. Simulation results for a 10 MHz prototype filter using AMI 0.5μm process is presented. The chip testing results show that the automatic frequency tuning error is 2.5% for the 10 MHz case.

A new tuning scheme for linearly tunable high-Q filters is proposed. The tuning method is based on using the phase information for both frequency and Q factor tuning. There is no need to find out the relationship between a filter's passband magnitude and Q. A gm-C biquadratic filter is designed to demonstrate the proposed tuning circuitry. The project includes a phase locked loop (PLL) based frequency tuning loop, reference clock generator, and differential difference amplifier (DDA) for dealing with frequency and Q factor tuning loop and linearly tunable second order gm-C bandpass filter. Simulation results for a 10 MHz prototype filter using AMI 0.5μm process is presented. The chip testing results show that the automatic frequency tuning error is 2.5% for the 10 MHz case.

In this thesis, a simple on-chip automatic frequency tuning circuit is presented. The tuning circuit is improved from voltage-controlled filter (VCF) frequency tuning circuit. We use a single time constant (STC) circuit to substitute the voltage-controlled filter. The STC circuit can produce a controllable delay time clock. The tuning circuit uses the constant delay time to tune the frequency of the filter. The design of a STC circuit is easy. Because the circuit is simple, the tuning circuit has less chip area and less power consumption. The circuit has been fabricated with 0.35£gm CMOS technology. It operates with supply voltages ¡Ó1.5 V. The filter operates at a 3-dB frequency of 10MHz. In simulation, the frequency tuning circuit has a 3-dB frequency tuning error of less than 12% and the power consumption less than 9.05mW over a range of supply voltages (¡Ó10%), operating temperatures (-20¢J to 70¢J) and five models of SPICE model.

Master of Science / Department of Electrical and Computer Engineering / William B. Kuhn / In microchip circuitry, the tiny size of inductors creates low Q values, limiting a bandpass filter’s ability to have narrow bandwidths at RF frequencies. To counter this problem and also compensate for losses, Q-enhancement can be implemented to facilitate narrower bandwidths and boost gain. With Q-enhancement, temperature sensitivity of the circuitry causes the filter parameters to drift over time, making it necessary to adjust the filter periodically in order to keep the filter centered at the desired frequency. With the proper additional on-chip circuits used with a microprocessor, a tuning algorithm makes it possible to automatically tune the filter in-situ. The algorithm is based on increasing Q-enhancement until the filter begins to oscillate, reading the frequency of oscillation, adjusting to the desired frequency, and then decreasing Q-enhancement until the filter no longer oscillates. A 500MHz single-pole differential filter was designed with an on-chip amplitude detector and frequency prescaler to facilitate tuning. The filter was made adjustable across frequency with banks of binary weighted switchable capacitors. Q-enhancement adjustment was achieved via banks of cross-coupled FETs, also binary weighted. The circuit was fabricated in 0.5μm silicon-on-sapphire technology. The finished filter chip was controlled with a PIC microprocessor which had been programmed in C with the tuning algorithm. With the tuning algorithm in place, the filter was successfully able to align itself to within ±1MHz of the desired 500MHz center frequency. Q-enhancement levels were also able to self-adjust to maintain a desired bandwidth. An improved design based around an off-chip coupled-resonator two-pole filter has also been designed. This filter includes adjustable coupling capacitance between the two poles, which also must be tuned. A new method of tuning is proposed for such applications. The properties of a two-pole filter cause it to oscillate at two frequencies with Q-enhancement. A modified amplitude detector is capable of reading the beat frequency which results from the two oscillations, a value which relates directly to and allows tuning of the bandwidth of the filter.

Over the last several decades we have witnessed tremendous change in the landscape of computer architecture. New architectures have emerged at a rapid pace with computing capabilities that have often exceeded our expectations. However, the rapid rate of architectural innovations has also been a source of major concern for the high-performance computing community. Each new architecture or even a new model of a given architecture has brought with it new features that have added to the complexity of the target platform. As a result, it has become increasingly difficult to exploit the full potential of modern architectures for complex scientific applications. The gap between the theoretical peak and the actual achievable performance has increased with every step of architectural innovation. As multi-core platforms become more pervasive, this performance gap is likely to increase. To deal with the changing nature of computer architecture and its ever increasing complexity, application developers laboriously retarget code, by hand, which often costs many person-months even for a single application. To address this problem, we developed a software-based strategy that can automatically tune applications to different architectures to deliver portable high-performance. This dissertation describes our automatic tuning strategy. Our strategy combines architecture-aware cost models with heuristic search to find the most suitable optimization parameters for the target platform. The key contribution of this work is a novel strategy for pruning the search space of transformation parameters. By focusing on architecture-dependent model parameters instead of transformation parameters themselves, we show that we can dramatically reduce the size of the search space and yet still achieve most of the benefits of the best tuning possible with exhaustive search. We present an evaluation of our strategy on a set of scientific applications and kernels on several different platforms. The experimental results presented in this dissertation suggest that our approach can produce significant performance improvement on a range of architectures at a cost that is not overly demanding.

<p>This master theses deals with different methods for automatic tuning of the existing controller for external axis. </p><p>Three methods for automatic tuning have been investigated. Two of these are based on the manuell method used today. The third method is based on optimal placement of the dominant poles. Different sensitivity functions are important for this method. </p><p>At the end of the thesis, a proposal of a complete tool for automatic tuning is given.</p>

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

This master theses deals with different methods for automatic tuning of the existing controller for external axis. Three methods for automatic tuning have been investigated. Two of these are based on the manuell method used today. The third method is based on optimal placement of the dominant poles. Different sensitivity functions are important for this method. At the end of the thesis, a proposal of a complete tool for automatic tuning is given.

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

In Scania’s single speed engines for industrial and marine use, the engine speed is controlled by a PI-controller. This controller is tuned independent of engine type and application. This brings certain disadvantages since the engines are used in a wide range of applications where the dynamics may differ. In this thesis, the possibility to tune the controller automatically for a specific engine installation has been investigated. The work shows that automatic tuning is possible. By performing an identification experiment on the engine, the parameters in a first order model describing the dynamics of the engine and the load aggregate are determined. The control parameters are then determined as functions of the model parameters. Measurements on a generator set show that the proposed method provides a controller which is able to follow changes in the reference value, and to compensate for load disturbances. / I Scania’s envarvsmotorer för industri- och marin-bruk regleras varvtalet av en PI-regulator. Denna regulator är inställd oberoende av motortyp och applikation. Detta medför vissa nackdelar då motorerna används i flera olika typer av applikationer där dynamiken kan variera. I detta arbete har det undersökts huruvida det är möjligt att automatiskt ställa in parametrarna i en PID-regulator för en enskild motorinstallation. Arbetet visar att automatisk inställning är möjlig. Genom att göra ett identifieringsexperiment på motorn bestäms parametrarna i en första ordningens modell som beskriver dynamiken för den aktuella konfigurationen av motor och belastande aggregat. Därefter bestäms regulatorparametrarna som funktion av modellparametrarna. Mätningar på ett generatoraggregat visar att man med hjälp av den föreslagna metoden erhåller en inställning av regulatorn som både klarar av att följa börvärdesförändringar och kompensera för laststörningar.