A 2.5V 8-bit 100MSample/sec folding and interpolation analog to digital converter is described in this thesis. First, a cascoding folding amplifier is used for improve power consumption. The differential pairs of the folding amplifier are cascoded to reduce the numbers of reference current source, so the power consumption is reduced. In order to reduce more power consumption, we drop the power supply down to 2.5V. However, the power supply is not large enough to keep the folding amplifier working normally and it causes the output signal aberration. Hence, we propose a back-end amplifier to connect the folding amplifier to overcome the problem. Therefore, the power consumption of all circuit is reduced to 15.292mW. Moreover, the capacitive loading at the output of the cascoded differential pairs is smaller than that of conventional cascaded differential pairs, and we employ a distributed folding technique to reduce the folding factors of each folding amplifier. Therefore, we improve the frequency multiplication effect to increase the analog input signal bandwidth. Beside, in order to heave the input signal range of the voltage mode comparator, we employ an n-channel input stage. Because the input signal range of n-channel is higher than that of p-channel input stage. By using these techniques, the input signal bandwidth and the power consumption of overall circuit are improved greatly. The proposed analog to digital converter is designed by TSMC 0.35£gm 2P4M CMOS process, and it operates at 2.5V power supply voltage with 1V to 2.4V reference voltage. The simulation results show that the power consumption is 15.292mW, DNL is +/- 0.55LSB, and INL is 1.7LSB ~ -0.8LSB.

In modern telecommunications, there is a need for quadrature oscillator exhibiting an accurate and stable phase relation. For example, identical two mutually coupled relaxation oscillator can generate identical quadrature signals, and have extremely accurate and stable phase relation. In this thesis, we propose a current cross-coupled relaxation oscillator with quadrature outputs. The oscillator consists of two identical current relaxation oscillators and a current comparator. The circuit takes the high frequency advantage of current mode circuit. Because of cross-coupled feedback, this oscillator have highly accurate ( <1¢X) and stable quadrature outputs. It is implemented by using TSMC 0.35£gm 2P4M CMOS technology.

Since the invention of SRAM (Static Random Access Memory), many improvements have been proposed. The major targets are speed, area, and power consumption. The evolution of the CMOS process technology makes it possible to implement SRAM by using dual threshold voltage transistors. Hence, we will use TSMC (Taiwan Semiconductor Manufacturing Company) 0.25 $mu$m 1P5M CMOS process to realize the dual threshold voltage SRAM in this thesis. In order to reduce SRAM internal power consumption, we also propose quenchers to suppress unwanted oscillation between bit lines. In addition, several types of BIST (Build In Self Test) comparators are also proposed to test the mentioned SRAM. After detailed simulations, the proposed comparators possess impressive results in high fan-in, low transistor count, and high speed. The proposed SRAM and BIST comparators are fabricated by the CMOS process provided by National Science Council Chip Implementation Center (CIC). The measurements of the chips are fully corrected to meet the design goals.

Three different topics associated with their respective applications are proposed in this thesis. The first application is the implementation of a fast tagged sorter. A novel and high-speed realization of the tagged sorting algorithm is presented. Meanwhile, the problems to detect whether the queue is empty or full is also resolved without increasing any hardware cost. The second topic is focused on the implementation of a fast dynamic 64-bit comparator with small transistor count. The entire 64-bit comparator is composed of equality comparators and zero/one detectors, which are proposed by C.-F. Wu. The problem to handle a large fan-in requirement is also resolved in our design. The third topic is to carry out a power demand monitor system for factories. Not only can it monitor the factory¡¦s power network with a graphical user interface, but also can turn off the unessential equipments automatically when the total power consumed by the factory is larger than what was expected.

Low dropout regulators (LDOs) are important components for power management in modern integrated circuits. With the continued scaling down of power supply voltage, digital LDOs have become a more attractive design choice since they avoid the difficulty of designing high-gain amplifiers with low voltage. This thesis investigates techniques for both modeling and enhancement of digital LDO transient response. It discusses the importance of the resistance in the output stage of an LDO, and proposes a simulation model for examining LDO transient response. In addition, the thesis studies circuit techniques to improve LDO transient response. Different LDO circuits are implemented and compared in this study.

<p>This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.</p><p>The comparator is designed for time-interleaved bandpass sigma-delta ADC.</p><p>Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed.</p><p>The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.</p>

This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V. The comparator is designed for time-interleaved bandpass sigma-delta ADC. Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed. The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.

The aim of my thesis is to consider the usage of PPP method by the reconstruction of the object of former prison in town Uherské Hradiště using the methodology of the Ministry of Finance of the Czech Republic. In the theoretical part the description of the PPP method and its features is given. In the practical part the simplified financial model for project is counted. The outcomes of the model should be taken from the public sector point of view as the basic source for making decision if PPP method is the most efficient for this project.

The minimalist state of the national treatment provision in the investment treaties has provided limited guidance for the tribunals for interpretation. As a result, there were inconsistencies in the interpretation of national treatment, in particular the question of likeness. This thesis aims to develop the doctrinal understanding of the determination of appropriate comparator guided by the underlying philosophies, historical evolution and relevant investment decisions. The methods applied in this thesis are doctrinal and comparative studies of international investment law and the compared jurisprudences. A major part of this thesis is dedicated to examine the comparison and relevance of the GATT/WTO, EU and international human rights law in the interpretation of discrimination based on nationality. The interpretative methods applied by the respective jurisprudences in determining likeness and related questions of legitimate regulatory measures are examined to see whether there are lessons that could be learnt in the interpretation of national treatment in investment law. The finding of this thesis confirms that there is potentially a range of insightful guidance from the jurisprudences under comparison which could provide a structured understanding of national treatment in international investment law. The observations put forth highlight the underlying philosophies and values of the national treatment principle in protecting the investors and addressing the host states’ regulatory needs. It reflects the contemporaneous development in international investment law and provides a positive response to public administrative principles benefited by way of international comparative administration law.

<p>Comparator is the main building block in an ADC architecture. Main purpose of the comparator is to compare a signal with a reference signal and produce an output depending on whether the input signal is greater or smaller than reference. Many architectures for comparators exist for various purposes. In this thesis, Latched comparator architecture is used for sigma delta modulator. This particular design has two main characteristics that are very important for sigma delta application. First characteristic is the cancellation of memory effect which increases the speed and reliability of the system and the second is, with this architecture, high sensitivity can be achieved.</p><p>The design and implementation of lathed comparator for sigma delta modulator is presented in this thesis work. Various non-linearities and performance parameters are discussed in detail. Practical implementation and circuit design issues are highlighted to achieve maximum sensitivity along with reasonable speed and accuracy.</p>