In modern telecommunications, there is a need for quadrature oscillator exhibiting an accurate and stable phase relation. For example, identical two mutually coupled relaxation oscillator can generate identical quadrature signals, and have extremely accurate and stable phase relation. In this thesis, we propose a current cross-coupled relaxation oscillator with quadrature outputs. The oscillator consists of two identical current relaxation oscillators and a current comparator. The circuit takes the high frequency advantage of current mode circuit. Because of cross-coupled feedback, this oscillator have highly accurate ( <1¢X) and stable quadrature outputs. It is implemented by using TSMC 0.35£gm 2P4M CMOS technology.

During the latest ten years, development in the industry of machine tools has been growing rapidly in our country. Since industry automation is highly demanded, the study about CNC is therefore extensively proceeded. Owing to request for higher quality, the machine tool must achieve the high speed and high precision. There are three factors in precise motion control : the accuracy of reference command, the design of servo control structure, and machine structure. However the part of machine structure attains to maturity. The design of the control system need to include good motion control and correct reference command. NURBS can represent analytic curves and free-form curves accurately and easily. Cross-coupled control is able to adjust the dynamic system of each axis to reduce the contour errors. It is expected to improve control performance in terms of contour errors by combine NURBS reference command and the cross-coupled control framework. Keywords¡Gmachine tool, NURBS, cross-coupled control

Using compact structure to improve the defect of traditional transmission line filter which size is too big or transmission line is too long. Two special structures are used to implement the filter that is smaller or superior characteristic. One of the two structures is called DGS that etched defect in the ground plane. The etched lattice shape for the transmission line consists of narrow and wide etched areas in backside metallic ground, which give rise to increasing the effective capacitance and inductance of a transmission line, respectively. Thus, by using this character, the low-pass filters are designed and implemented easily. Another structure is coupled of microstrip square open-loop resonators. First, the coupling coefficients of the three basic coupling structures versus distance between adjacent resonators and different offset is established by means of three-dimensional field analysis methods. Then, the band-pass filter will be implemented by the combination of three basic coupling structures. Finally, two low-pass filter which have cutoff frequency 5.4GHz¡B2.26GHz and a four-pole band-pass filter are designed and fabricated. All theoretical and experimental performance is presented.

As the electronic products are gotten smaller and the quantity of output is to be requested, the trend of the needs for speed and accuracy is more precise. Therefore, upgrading the speed and the accuracy of contour error on tracking control has become an important point. This research is focus on the improvement of tracking error and contour error. In tracking error, we propose that the compensation of friction disturbance is by building friction model. And then adaptive robust controller is used to eliminate other disturbance. Finally, velocity feedforward controller is used to improve system dynamic response and to remove the effect of time delay. The combination of such controllers can improve tracking error directly and contour error indirectly. In contour error, we use cross-coupled controller to coordinate the motors and to reform contour error. On the association of such controllers, we propose the design method of cross-coupled controller, to replace the traditional way of try-and-error, and improving contour error again. Finally, the above improving strategies are verified by the simulation and experimental results.

As the electronic products are getting more and more small, the trend of the needs for speed and accuracy is more precise. Therefore, upgrading the speed and the accuracy of contour error on tracking control has become an important point. This research is focus on the improving of contour error and terminus error. In the contour error, we design the acceleration /deceleration profile based on digital FIR filter. And then remodel the compensatory method of cross-coupled controller, making the design of controller parameter easier, and getting better efficiency. And further, we get the time-variable gain by curve of contour error, making the accuracy better. In terminus error, according to two-step control, we switch the controller in deceleration region, not only directly improving the terminus error, but also improving the contour error. Finally, the above improved strategies are verified by the simulation and experimental results.

Because of IC technology evolution and the increase of market demand, the communication industry grows vigorously in recent years. The voltage-controlled oscillator plays a key role in the RF transceiver and provides oscillation signals needed for upconversin and downconvertion. Usually, we separate the signals into I/Q channels for modulation and demodulation in upconversin and downconvertion. Because the quality of the local oscillator influences the performance of communication system, designing a voltage-controlled oscillator that can provide two identical signals in accurate quadrature is necessary. In this thesis, a new quadrature voltage-controlled oscillator is presented. We use two identical relaxation oscillators with adjustable Schmitt triggers to construct the cross-coupled architecture. This oscillator has accurate ( <1¢X) and stable quadrature outputs which are independent of operating frequency and process variations. This oscillator circuit is fabricated in TSMC 0.35£gm CMOS Mixed-Signal process provided by National Chip Implementation Center (CIC). Our design is verified by simulation and measurement results.

Due to the demand for low-cost, small-form factor and large-scale integration of system-on-chip wireless transceivers, the image-reject, zero-IF and low-IF receiver architectures have become the main topologies used in mainstream wireless communication systems. Consequently, signal sources with quadrature phase outputs [quadrature oscillators (QOs)] are therefore essential, and their phase noise, driving capability, tuning range, oscillation frequency, and power consumption have a major impact on the overall receiver performance. Additionally, it is required that the QO synthesize precise I/Q waveforms across the signal bandwidth over process, voltage, and temperature variations for adequate image-rejection and signal modulation/demodulation. While the use of symmetrical layout and large inter-digitated devices minimize both systematic and random mismatches, this solution alone may not succeed in achieving the stringent performance requirements dictated by modern wireless standards particularly as the technology scales into the sub-100nm regime, necessitating both phase and gain calibration of the mismatched I/Q channels post-fabrication. Given the necessity for precise RF quadrature signal synthesis, the goal of this work is to investigate low-power low-phase-noise quadrature oscillator (QVCO) topologies with an integrated phase calibration feature. The first part of this work focuses on the analysis and modeling of cross-coupled LC QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, design trade-offs, phase-noise performance, effect of including phase shift in the coupling paths, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. Particularly, we introduce the concept of an effective core and coupling transconductances to explain various oscillator properties. Additionally, a new incremental circuit element — the quadrature resistance — is introduced to evaluate the effect of coupling on the open-loop quality factor and hence on the oscillator phase noise performance. Mechanisms affecting the mode selectivity are identified and modeled. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation. Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based on the disconnected-source parallel-coupled LC QVCO topology. The phase-tunable LC QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the relative amplitude error or consuming additional power or chip area. Additionally, in restoring the phase balance, it is observed that the proposed method restores the phase noise performance to its optimal value which presents a potential advantage over classical calibration techniques. Time domain measurements performed on a 5 GHz prototype show that I/Q signals with phase error up to ~±30°, beyond which the VCO cores are unlocked, can be driven to perfect quadrature phase. The PT-QVCO can be tuned from 3.87-4.45 GHz at the negative mode and 4.4-5.4 GHz at the positive mode, a total of ~1.5 GHz. The fabricated circuit including pad structures occupies an area of 1.1x0.7 mm² and drains 18mW (excluding buffer circuits) from a 1.8 V supply voltage. The third part of this work introduces a new low-power, low-phase-noise super harmonic injection-coupled LC QVCO (IC-QVCO) topology. Analysis of the waveform accuracy reveals an inverse dependence of the quadrature error on the tank quality factor thus allowing circuit optimization for both low phase noise and precise quadrature synthesis. Additionally, a tunable tail filter (TTF) is incorporated to calibrate the residual quadrature imbalance in presence of a 3-σ variation in the device parameters. An X-band IC-QVCO prototype with a TTF implemented in a 0.18μm RF CMOS process, achieves a measured phase noise figure-of-merit ranging from 177.3 to 182.6 dBc/Hz along the 9.0 to 9.6 GHz frequency tuning range while dissipating only 9mW from the 1.8V supply. The TTF reduces both the 1/f² and 1/f³ phase noise and calibrates the residual phase error within ±11° post-fabrication without affecting the relative amplitude error or the phase noise performance. The circuit performance compares favorably with recently published work. In the fourth part of this work, we explore the implementation of LC QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an MOS varactor and a digitally controlled switch capacitor array for frequency tuning, we propose an alternative frequency tuning technique based on the fundamental operation of LC QVCOs. The off-resonance operation, which is defined by the coupling network, suggests varying the coupling current to achieve frequency tuning. In essence, by modifying the bias current of the coupling transistors (G_Mc-tuning), a wide and linear frequency tuning range can be achieved. Extensive simulation results of a 60 GHz prototype, implemented in a 90 nm commercial RF CMOS process, demonstrates a 5 GHz of frequency tuning range (57.5 GHz → 62.5 GHz), a tuning sensitivity of 1GHz/mA, and a 4dB improvement in the phase noise compared to a varactor solution. Finally, the Appendix includes recent research work on the analysis and design of g<sbu>m</sub>-boosted common-gate low-noise amplifiers (CG-LNAs). While this topic seems to diverge from the main theme of the dissertation, we believe that the comprehensive analysis and the originality of the circuit design introduced in this work are worth acknowledging. / Ph.D. / While resting in bed due to illness, the Dutch scientist Christiaan Huygens keenly observed that the pendulums of two clocks hanging on the wall moved synchronously when the clocks were hung close to each other. He concluded that these two oscillatory systems were forced to move in unison by virtue of mechanical coupling through the wall. In essence, each pendulum injected mechanical vibrations into the wall that was strong enough to lock the adjacent pendulum into synchronous motion. Injection locking of oscillatory systems plays a critical role in communication systems ranging from frequency division, to generating clocks (oscillators) with finer phase separation, to the synthesis of orthogonal (quadrature) clocks. All communication systems have the same basic form. Firstly, there will some type of an information or data source which can be a keyboard or a microphone in a smartphone. The source is connected to a receiver by some sort of a channel. In wireless systems, the channel is the air medium. Moreover, to comply with the FCC and 3GPP requirements, data can only be transmitted wirelessly within a predefined set of frequencies and with stringent emission requirements to avoid interference with other wireless systems. These frequencies are generated by high fidelity clock sources, also known as oscillators. Consider a group of people sharing the same room and hence the same channel want to share information. Without regulating the “loudness” of each communicating ensemble, the quality of communication can be severely impaired. Moreover, it is to be expected that information can be shared more efficiently if each pair is allocated non-overlapping timeslots – speak when others are quiet. Called time orthogonality, all wireless systems require precise orthogonal (quadrature) clock sources to improve the communication efficiency. The precision of quadrature clocks is determined by the amplitude and phase accuracy. This dissertation takes a deep dive into the analysis and implementation of high accuracy quadrature (I/Q) clock sources using the concept of injection locking. These I/Q clocks or oscillators, also known as quadrature voltage controlled oscillators (QVCOs), have gained enormous popularity in the last decade. The first part of this work focuses on the analysis and modeling of QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation. Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based The phase-tunable QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the oscillator other performance metrics. The proposed topology was successfully verified in silicon using a 5GHz prototype. The third part of this work introduces a new low-power, low-phase-noise injection coupled QVCO (IC-QVCO) topology. An X-band IC-QVCO prototype was successfully verified in a 0.18m RF CMOS process. In the fourth part of this work, we explore the implementation of QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an conventional frequency tuning techniques, we propose an alternative approach based on the fundamental operation of QVCOs that outperforms existing solutions.

The objective of this thesis is to introduce novel procedures and guidelines to design bandstop microwave filters for modern terrestrial and satellite wireless communication systems. Among all available microwave filter technologies, planar structures of microstrip and substrate integrated waveguide (SIW) are chosen, due to ease of fabrication, low profile, weight and manufacturing cost. Particularly, SIW structures are more attractive because they have a better insertion loss, quality factor, and power handling capability in comparison to their microstrip counterparts, and can also be easily integrated into other planar circuitries. A comprehensive hybrid analytic-optimization method is developed to synthesize any single-band as well as multi-band bandstop coupling matrix. In this method, the location of reflection zeros (RZs) and the attenuations in stopbands can be determined in advance. Several novel single-band, dual-band, and triple-band bandstop filters are designed using regular and ridged SIW resonators, in-line coupled singlet resonators, cross-coupled resonators, and bandstop stubs. The designed filters have fractional bandwidths up to 23% . Moreover, a tunable ridged SIW bandstop resonator and a tunable CPW resonator, etched into the top plate of the SIW transmission line, are introduced. Combining these two resonators, a dual-band SIW filter is designed that permits one of its stopband to be tuned while another stopband is fixed. All introduced filters in this thesis are verified by commercial electromagnetic software, analytic investigations using Matlab codes, and measurements. / Graduate

Σε αυτήν την εργασία μελετήθηκε και σχεδιάστηκε ένας ψηφιακά ελεγχόμενος ταλαντωτής (DCO) με σκοπό GSM εφαρμογή. Οι συχνότητες λειτουργίας κυμαίνονται στο φάσμα 1.6GHz – 2GHz με βήμα 20kHz. Ο θόρυβος φάσης ποσοτικοποιείται στα -160dB/Hz σε 20 MHz απόκλιση. Ο έλεγχος του DCO γίνεται πλήρως ψηφιακά επιτρέποντας την υλοποίηση πλήρους ψηφιακού βρόχου κλειδώματος φάσης (ADPLL) και καθολικού system on chip design (SoC). Ο ταλαντωτής καταναλώνει 4,5 mWatt με 3,76 mA ρεύμα σε 1.2 V τροφοδοσία. / A Digitally Controlled Oscillator is studied and designed for GSM application. The operating frequencies are 1.6-2GHz with tuning range of 400MHz and finest step size 20 KHz. A fully digital control is achieved form where arises the opportunity for fabrication of an All-Digital Phase Locked Loop (ADPLL) and the whole system on chip (SoC). The proposed DCO core consumes 3.76mA from a 1.2V supply.

Rapid growth in the field of communications industry has led to newer opportunities and challenges in the design of CMOS based monolithic integrated circuits. ASK modulators are a class of digital modulators which are known for their relative simplicity of implementation for low cost applications in the industrial and biomedical domains. This thesis presents a LC-based CMOS Amplitude Shift Keying (ASK) modulator scheme which demonstrates promising capability for radio frequency designs. This work describes the design and implementation of differential cross-coupled NMOS only LC power oscillator with ASK modulation to operate at 2.4 GHz frequency. In this work, 65nm CMOS process technology has been used for implementation. The work mainly focused on system parameters such as oscillation frequency, output signal power, power consumption and phase noise. The LC tank was created with a centre-tap on-chip differential spiral inductor and a Metal Insulator Metal (MIM) capacitor. The method of a current mirror with switching technique is employed for biasing the LC oscillator as well as ASK modulation output. The oscillator circuit has been optimised by using a simulation based approach to study the design and measurements to gain a greater insight into the performance of the ASK modulator. An output signal power of -1.59dBm at 2.30 GHz with a phase noise of -115.39dBc/Hz@1MHz and a power consumption of 5.92mW has been achieved at the layout level. Optimal ASK modulated output performance has been obtained for the data rate of up to around 40Mbits/s. In this thesis, simulation results have been presented for both the schematic and the layout levels.