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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Design of a Differential Cross-Coupled Power LC Oscillator with ASK Modulation

Sarker, Sanjay January 2023 (has links)
Rapid growth in the field of communications industry has led to newer opportunities and challenges in the design of CMOS based monolithic integrated circuits. ASK modulators are a class of digital modulators which are known for their relative simplicity of implementation for low cost applications in the industrial and biomedical domains. This thesis presents a LC-based CMOS Amplitude Shift Keying (ASK) modulator scheme which demonstrates promising capability for radio frequency designs. This work describes the design and implementation of differential cross-coupled NMOS only LC power oscillator with ASK modulation to operate at 2.4 GHz frequency. In this work, 65nm CMOS process technology has been used for implementation. The work mainly focused on system parameters such as oscillation frequency, output signal power, power consumption and phase noise. The LC tank was created with a centre-tap on-chip differential spiral inductor and a Metal Insulator Metal (MIM) capacitor. The method of a current mirror with switching technique is employed for biasing the LC oscillator as well as ASK modulation output. The oscillator circuit has been optimised by using a simulation based approach to study the design and measurements to gain a greater insight into the performance of the ASK modulator. An output signal power of -1.59dBm at 2.30 GHz with a phase noise of -115.39dBc/Hz@1MHz and a power consumption of 5.92mW has been achieved at the layout level. Optimal ASK modulated output performance has been obtained for the data rate of up to around 40Mbits/s. In this thesis, simulation results have been presented for both the schematic and the layout levels.

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