Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers. The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. ¢Ï synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators.

Since the invention of SRAM (Static Random Access Memory), many improvements have been proposed. The major targets are speed, area, and power consumption. The evolution of the CMOS process technology makes it possible to implement SRAM by using dual threshold voltage transistors. Hence, we will use TSMC (Taiwan Semiconductor Manufacturing Company) 0.25 $mu$m 1P5M CMOS process to realize the dual threshold voltage SRAM in this thesis. In order to reduce SRAM internal power consumption, we also propose quenchers to suppress unwanted oscillation between bit lines. In addition, several types of BIST (Build In Self Test) comparators are also proposed to test the mentioned SRAM. After detailed simulations, the proposed comparators possess impressive results in high fan-in, low transistor count, and high speed. The proposed SRAM and BIST comparators are fabricated by the CMOS process provided by National Science Council Chip Implementation Center (CIC). The measurements of the chips are fully corrected to meet the design goals.

This thesis includes two topics. One is a low-power high-speed 8-bit pipelining CLA design using dual threshold voltage (dual- Vth) domino logic. The other is a low-cost digital I/Q separator for DVB-T receivers. A high speed and low power 8-bit CLA using dual- Vth domino logic blocks arranged in a PLA-like style with pipelining is presented. According to parallely precharge and sequentially evaluate in a cascaded set of domino logic blocks, transistors in the precharge part and the evaluation part of dual- Vth domino logic are, respectively, replaced by high Vth transistors to reduce subthreshold leakage current through OFF transistors, and low Vth transistors. Moreover, an nMOS transistor is inserted in the precharge phase of the output inverter such that the two-phase dual- Vth domino logic can be properly applied in a pipeline structure. Consequently, the proposed design keeps the advantage of high speed while attaining the effect of low power dissipation. A low-cost digital I/Q separator is presented in the second part of this thesis. Using digital I/Q separator in place of the traditional analog I/Q separator guarantees the design conquer gain and phase mismatch problems between the I and Q channels. The proposed design can berealized by inverters and shifters such that the goal of low cost can be achieved.