Two novel clock feedthrough compensation circuits for switched - current (SI) memory cells are proposed to reduce the clock feedthrough error. One is a current compensation first generation SI memory cell and another is an error voltage reduction second generation SI memory cell. Both circuits are designed using a 0.5£gm UMC CMOS process. In this study, the first circuit has obtained an accuracy about 0.1% error with a frequency of 5MHz, and the second circuit has achieved 0.12% error in accuracy with 10.5MHz in frequency. The results are obtained by SPICE simulates.

In this thesis, a switched-current integrator with active amplifier feedback and dummy switch is proposed to increase the operation speed and reduce the non-ideal effects in traditional switched-current circuit. The active amplifier is designed in low gain and high bandwidth so that the oscillation can be avoided. We improve the operation speed and transmission error by the active amplifier feedback and reduce the CFT error by the dummy switch so that high resolution can be achieved. Then we apply the proposed integrator to the switched-current sigma-delta modulator. The sigma-delta modulator is simulated using TSMC 0.35£gm CMOS process with 3.3V power supply. We obtain 67dB PSNR, 66dB dynamic range(DR), and 40KHz bandwidth. The sampling frequency is 10.24MHz, the power supply is 3.3V and the power consumption is 19mW.

In this thesis, a switched-current sample-and-hold circuit is proposed. We use feedback circuit to decrease the input impedance and to reduce the transmission error in SI cell. Furthermore, the entire memory cell is designed in a coupled differential replicate form to eliminate the clock feedthrough (CFT) error. The sample-and-hold circuit is simulated using the parameters of TSMC 0.35£gm CMOS process. The simulation results show that the spurious-free dynamic range (SFDR) is 55 dB, the sampling rate is 40MHz, the power consumption is 0.38 mW, and the power supply is 1.5V. Furthermore, the circuit is verified by cadence-hspice simulation.

The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator. The proposed Sigma Delta modulator uses TSMC 0.18£gm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.

In this thesis, a switched-current sigma-delta modulator (SDM) with op-amp active integrator is proposed. The major study is focused on using the op-amp to reduce the input impedance for high speed and high solution and utilizes the dummy switch to decrease the clock feedthrough (CFT) error. We use a sample-and-hold circuit which consists of an op-amp active memory cell and a dummy switch circuit to implement the integrator. It is applied to the building blocks of SDM. The modulator is a second order sigma-delta modulator. A current comparator transforms the current signal into digital voltage signal. A single-bit digital-to-analog (D/A) feedback circuit is used to convert the one-bit digital output to the SI integrator .The modulator is designed in the current mode technique. The delta-sigma modulator simulates using the parameters of the TSMC 0.35£gm CMOS process. The simulation results show that the signal to noise plus distortion ratio (SNDR) is 72 dB, the sampling rate is 10.24MHz, the oversampling ratio is 128, the power consumption is 21mW, the dynamic range is about 70dB, and the power supply is 3.3V. Furthermore, the circuit is verified by cadence-hspice simulation.

Conselho Nacional de Desenvolvimento Científico e Tecnológico / Circuits for sampling and retention of analogue signals are commonly implemented with techniques such as switched capacitors (SC). SC circuits employing the storage of charge in a linear capacitor to represent a signal in the form of voltage. Operational Amplifiers (AmpOp's) are used to transfer the load of a capacitor to another, sampling and holding circuits for analogue signals in closed loop. Recently, another technique has been developed without the need of building linear capacitors, making possible projects compatible with VLSI CMOS processes. This technique, called Switched Current (SI), is characterized by processing the signals in the current form, and implemented through the memory retention of electric charge on the gate of a MOS transistor in saturation zone. The charge is hold in a gate-source voltage and hence the current in a transistor. In this model, the excursion of the signal is not directly dependent on the supply voltage, but dependent on the polarization and current signal. This makes the model attractive for low voltage. The technique does not require AmpOp's and capacitors. The speed of the circuit is not limited by AmpOp's and its gainbandwidth product, but by design and manufacturing process. This technique is not yet consolidated and its performance is still not competitive with SC circuits [1] However, SI circuits become interesting as they constitute an open field for future research and the opportunity to be fully implemented in processes manufacturing oriented to purely digital circuits. This work begins with a framework of the subject matter, placing the reader in the state of the art manufacturing technology and some implications that directly affect analog circuits. Are also presented in this section some implementations which serve to characterize what is being done recently in terms of Sigma Delta (ΣΔ) modulators. Abstract vi In Chapter 2, are made a review of sampling and holding bases, the AD conversion techniques with focuses in oversampled AD converters, the circuits that implementing SC and SI modulators and their influences, and finally a review of the nonidealities that involve the practice of project. Chapter 3 a comparative study is done between memory cells SC and SI. Based on a simplified model of small signals, the behavior analyzes on the signal-noise-ratio (SNR), power consumption and speed, providing indications of performance throughout the operating region of MOS transistors. Chapter 4 deals with the initial specifications for the development of a ΣΔ AD converter for a specific implementation. The s tudies and estimates lead to pre-design of the project's ultimate goal the creation of a ΣΔ modulator in the SC and SI techniques. In Chapter 5 is intended to make the measures and tests that establish the standards of comparison, the discussion of results and conclusions. Finally, in Chapter 6, an alternative proposal is presented based on an architecture that performs a sigma-delta modulator with low distortion, implemented with SI circuit. The final conclusions and contributions are presented in Chapter 7. / Circuitos de amostragem e retenção de sinais analógicos são comumente implementados com técnicas de chaveamento de capacitores (Switched Capacitor SC). Circuitos SC empregam o armazenamento de cargas em um capacitor linear para representar um sinal sob a forma de tensão. Amplificadores Operacionais (AmpOp s) são usados para transferir essa carga de um capacitor a outro, amostrando e retendo sinais analógicos em circuitos de malha fechada. Recentemente, uma outra técnica tem sido desenvolvida sem a necessidade de construção de capacitores lineares, tornando possíveis projetos compatíveis com processos de fabricação VLSI CMOS. Esta técnica, chamada de Switched Current (SI), caracteriza-se por processar os sinais sob a forma de correntes, sendo a operação de memorização implementada através da retenção de carga elétrica na porta de um transistor MOS na zona de saturação. A carga retida corresponde a uma tensão portafonte e, conseqüentemente, a uma corrente no transistor. Neste modelo, a excursão do sinal não é diretamente dependente da tensão de alimentação, mas dependente das correntes de polarização e de sinal. Isso torna o modelo atrativo para baixas tensões. A técnica não requer AmpOp s e implementação física de capacitores. A velocidade do circuito não é limitada por AmpOp s e seu produto ganho-banda, mas pelo projeto e processo de fabricação. Essa técnica ainda não está consolidada e sua performance ainda não é competitiva com os circuitos SC [1], Contudo, os circuitos SI tornam-se interessantes na medida em que constituem um campo aberto para futuras pesquisas e pela possibilidade de serem completamente implementados em processos de fabricação voltados a circuitos puramente digitais. Este trabalho inicia com um enquadramento do trabalho proposto, situando o leitor no contexto do estado da arte das tecnologias de fabricação e algumas implicações diretas que afetam circuitos analógicos. São apresentadas ainda nesta seção algumas implementações que servem para caracterizar o que está sendo feito recentemente em termos de conversores tipo Sigma Delta (ΣΔ). No Capítulo 2, faz-se o embasamento sobre as técnicas utilizadas no processo de amostragem e retenção utilizadas para conversão ADΣΔ e uma revisão das não idealidades que envolvem a prática de projeto. No Capítulo 3 é feito um estudo comparativo, entre células de memória SC e SI. Baseado em modelo simplificado de pequenos sinais, analisa-se o comportamento quanto à relação-sinal-ruido (SNR), ao consumo e à velocidade, fornecendo indicações de desempenho em toda região de funcionamento dos transistores MOS. No Capitulo 4 são abordadas as especificações iniciais ao desenvolvimento de um conversor ΣΔ para uma implementação específica. Os estudos e estimativas que conduzem a pré-concepção do projeto têm como objetivo final a geração de um modulador ΣΔ nas técnicas SC e SI. Nos Capítulos 5 efetuam-se as medidas e testes que estabelecem os padrões de comparação, a discussão dos resultados e conclusões. Por fim, no Capítulo 6, uma proposta alternativa é apresentada com base em uma arquitetura de modulador sigma-delta de baixa distorção, implementada em circuito SI. As conclusões e contribuições finais são apresentadas no capítulo 7.

The increasing complexity of digital circuits forces the use of new technologies. New technologies have the advantage of reducing the circuit size and power consumption coupled with operation speed increasement. Most of signal processing operations migrated to the digital domain, thus, basic blocks like AD converters are needed in mixed-signal systems. Analog-todigital converters based on Sigma-Delta (ΣΔ) modulators stand out among the existing architectures because they cover a wide range of applications. The most common implementation of ΣΔ modulators in CMOS technology is based in switched-capacitor technique (SC), mainly due to its high performance and excellent linearity. However, the continuous reduction in the transistor physical dimensions requires a proportional reduction in the supply voltage levels, making difficult the design of analog circuits with conventional topologies. To overcome this problem, design techniques to analog circuits compatible with these new technologies were developed. This is the case of the technique known as switched-current (SI), which uses samples in the current domain to represent the signal information. This work presents the design of a switched-current Sigma-Delta modulator (SI-ΣΔM) using an architecture oriented to low-distortion applications. The architecture s main characteristic is the reduced sensitivity to integrator nonlinearities, leading to a significant increase in the signal-to-noise ratio (SNR) and dynamic range (DR) values, moreover, it permits the design of high-order modulators intrinsically stable. To demonstrate and verify the performance of the used strategy, based on a combination of circuit techniques and topology, a cascade 2-2 SI-ΣΔM was designed in a CMOS XFAB XC06 technology. Postlayout simulations show that the SNR reaches a maximum value of 80 dB and a dynamic range of approximately 87 dB, implying an effective resolution of 14.15 bits considering 20 kHz bandwidth. The prototype was sent to manufacturing and will be subject to laboratory tests when it returns. / A crescente complexidade dos circuitos digitais força o uso de novas tecnologias de fabricação. A mudança para tecnologias mais avançadas tem como vantagem a redução do tamanho do circuito e a diminuição do consumo de energia aliados ao aumento da velocidade de operação. Grande parte das operações envolvendo processamento de sinais migraram para o domínio digital, portanto, blocos básicos como conversores AD são necessários em sistemas de sinal misto. Conversores AD com base em moduladores do tipo Sigma-Delta (ΣΔ) destacam-se entre as arquiteturas existentes por cobrir uma ampla gama de aplicações. A implementação mais usual de moduladores ΣΔ em tecnologia CMOS baseia-se na técnica de capacitor-chaveado (SC), devido, principalmente, à sua elevada performance e excelente linearidade. Entretanto, a contínua redução das dimensões físicas dos transistores tem exigido uma redução proporcional dos níveis de tensão de alimentação, dificultando o projeto de circuitos analógicos com topologias convencionais. Para contornar este problema, técnicas de projeto de circuitos analógicos compatíveis com essas novas tecnologias foram desenvolvidas. Este é o caso da técnica conhecida como corrente chaveada (SI), que utiliza amostras sob a forma de corrente para a representação de sinais. Neste trabalho é apresentado o projeto de um modulador ΣΔ em modo corrente (SI-ΣΔM) empregando uma arquitetura orientada à aplicações de baixa distorção. Esta arquitetura tem como principal característica a reduzida sensibilidade às não-linearidades do integrador, conduzindo a uma significante melhora no valor da relação sinal-ruído (SNR) e faixa de excursão dinâmica (DR), além de permitir a concepção de moduladores ΣΔ de elevada ordem intrinsecamente estáveis. Para demonstrar e comprovar a performance da estratégia empregada, baseada na combinação de técnicas de circuito e de topologia, projetou-se um modulador SI-ΣΔ cascata 2-2 na tecnologia XFAB CMOS XC06. Simulações elétricas pós-layout revelam que o SNR atinge um valor máximo de 80 dB e uma faixa dinâmica de aproximadamente 87 dB, inferindo uma resolução efetiva de 14,15 bits considerando uma banda de interesse de 20 kHz. Por fim, o protótipo desenvolvido foi enviado para fabricação e será alvo de testes em laboratório quando retornar.

The work deals with design and realisation of the five-levels high-speed quantizer using switched-current technique (SI). The main aim is to use an advantage of switched-current technique like potential of the high-speed operation and to minimize disadvantages at all. Flash structure of the quantizer is used to ensure high-speed operation. It is supposed that the quantizer will be part of greater integrated systems such as higher-order delta-sigma modulators. Simulations are performed in CADENCE simulation tool using AMIS CMOS 0,7 µm technologic process.

The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.

The thesis focuses on a higher order noise-shaping Δ ADC architecture which employs filtered quantization error as a dither signal. Furthermore, the work studies implementation challenges using Switched-Capacitor and Switched-Current techniques. Digitization in an IF conversion receiver can be accomplished either with a wide band Nyquist rate ADC or a BandPass Δ ADC. The use of the latter is the optimum solution since the bandwidth of the IF signals is typically much smaller than the carrier frequency and reducing the quantization noise in the entire nyquist band becomes superfluous. Instead by using BandPass Δ ADCs the quantization noise power is reduced only in a narrow band around IF location. We study state-of-the-art high dynamic range Δ data converter topologies suited for wide-band radio receivers. We propose a topology which achieves higher order noise shaping by employing filtered quantization error as a dither signal. We study implementation challenges for Δ converters in digital technology. Traditionally, Δ ADCs used Switched-Capacitor (SC) circuits to realize their building blocks. This analog sample-data technique is based on the idea that a periodically switched capacitor can emulate a resistor. The limiting factor that degrades the performance of SC circuits implemented in standard VLSI technologies is the continuous reduction of supply voltages, prompted by the continuous scaling-down process. This fact, which is advantageous for digital circuitry, makes the design of SC circuits difficult, which are forced to use clock boosting strategies for switches and to increase the power consumption in order to obtain high-speed and high dynamic range opamps with low voltage operation. In this scenario, the use of current-domain sampled data technique, also named Switched-Current (SI), instead of voltages results advantageous for several reasons. As the signal carriers are currents, the supply voltage does not limit the signal range as much as in SC circuits. Therefore, SI circuits are more suitable than SC for low-voltage operation. This work studies the feasibility and bottlenecks of implementing Δ modulator building blocks using SI technique. A BandPass filter, DAC and 1-bit quantizer have been designed in 0.18µm technology using SI technique. (For mathematical equations pl refer the pdf file)