In this thesis, a switched-current sample-and-hold circuit is proposed. We use feedback circuit to decrease the input impedance and to reduce the transmission error in SI cell. Furthermore, the entire memory cell is designed in a coupled differential replicate form to eliminate the clock feedthrough (CFT) error. The sample-and-hold circuit is simulated using the parameters of TSMC 0.35£gm CMOS process. The simulation results show that the spurious-free dynamic range (SFDR) is 55 dB, the sampling rate is 40MHz, the power consumption is 0.38 mW, and the power supply is 1.5V. Furthermore, the circuit is verified by cadence-hspice simulation.

The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator. The proposed Sigma Delta modulator uses TSMC 0.18£gm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.