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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Projects in the Design and Construction of a Scanning Tunneling Microscope and UHV Sample Analysis Chamber

Oakes, Patrick W January 2004 (has links)
Thesis advisor: Vidya Madhavan / Three projects have been undertaken during the design and the construction of a scanning tunneling microscope. The first project focuses on a method of testing the movement of piezoelectric ceramics by means of a modified Michelson interferometer. These tests determine the magnitude and the direction of motion on the scale of a few angstroms. These piezos are then used in moving the tip of the STM. The second project concerned the design of a surface analysis chamber to be used for thin film depositions. This chamber will operate at UHV levels and will produce samples to be examined by the STM. The final project dealt with the construction and testing of a feedback loop to be used in the e-beam heater during thin film depositions. This box monitors the current between the sample and the source modifying the voltage across the filament to ensure the current between the two remains constant, ensuring a constant deposition rate. / Thesis (BS) — Boston College, 2004. / Submitted to: Boston College. College of Arts and Sciences. / Discipline: Physics. / Discipline: College Honors Program.
2

A Low Voltage Class AB Switched Current Sample and Hold Circuit

Hung, Ming-yang 21 August 2009 (has links)
In this thesis, a switched-current sample-and-hold circuit is proposed. We use feedback circuit to decrease the input impedance and to reduce the transmission error in SI cell. Furthermore, the entire memory cell is designed in a coupled differential replicate form to eliminate the clock feedthrough (CFT) error. The sample-and-hold circuit is simulated using the parameters of TSMC 0.35£gm CMOS process. The simulation results show that the spurious-free dynamic range (SFDR) is 55 dB, the sampling rate is 40MHz, the power consumption is 0.38 mW, and the power supply is 1.5V. Furthermore, the circuit is verified by cadence-hspice simulation.

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