Semiconductor nanotechnology is today a very well studied subject, and demonstrations of possible applications and concepts are abundant. However, well-controlled mass-fabrication on the nanoscale is still a great challenge, and the lack of nanofabrication methods that provide the combination of required fabrication precision and high throughput, limits the large-scale use of nanodevices. This work aims in resolving some of the issues related to nanostructure fabrication, and deals with development of nanofabrication processes, the use of size-reduction for reaching true nanoscale dimensions (20 nm or below), and finally the optical and electrical characterization to understand the physics of the more successful structures and devices in this work. Due to its widespread use in microelectronics, silicon was the material of choice throughout this work. Initially, a fabrication process based on electron beam lithography (EBL) was designed, allowing controlled fabrication of devices of dimensions down to 30 nm, although, generally, initial device dimensions were above 70 nm, allowing the flexible but low-throughput EBL, to be replaced by state-of-the-art optical lithography in the case of industrialization of the process. A few main processes were developed throughout the course of this work, which were capable of defining silicon nanopillar and nano-wall arrays from bulk silicon, and silicon nanowire devices from silicon-on-insulator (SOI) material. Secondly, size-reduction, as a means of providing access to few-nanometer dimensions not available by current lithography techniques was investigated. An additional goal of the size-reduction studies was to find self-limiting mechanisms in the process, that would limit the impact of variations in the size and other imperfections of the initial structures. Thermal oxidation was investigated mainly for self-limited size-reduction of silicon nanopillars, resulting in well-defined quantum dot arrays of few-nm dimensions. Electrochemical etching was employed to size-reduce both silicon nanopillars and silicon nanowires down into the 10-nm regime. This being a novel application, a more thorough study of electrochemical etching of low-dimensional and thin-layer structures was performed as well as development of a micro-electrochemical cell, enabling electrochemical etching of fabricated nanowire devices with improved control. Finally, the combination of nanofabrication and size-reduction resulted in two successful device structures: Sparse and spatially well-controlled single silicon quantum dot arrays, and electrically connected size-reduced silicon nanowires. The quantum dot arrays were investigated through photoluminescence spectroscopy demonstrating for the first time atomic-like photoemission from single silicon quantum dots. The silicon nanowire devices were electrically characterized. The current transport through the device was determined to be through inversion layer electrons with surface states of the nanowire surfaces greatly affecting the conductance of the nanowire. A model was also proposed, capable of relating physical and electrical properties of the nanowires, as well as demonstrating the considerable influence of charged surface states on the nanowire conductance. / QC 20101101
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:kth-420 |
| Date | January 2005 |
| Creators | Juhasz, Robert |
| Publisher | KTH, Mikroelektronik och Informationsteknik, IMIT, Stockholm : KTH |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Doctoral thesis, comprehensive summary, info:eu-repo/semantics/doctoralThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | Trita-FTE, 0284-0545 ; 2005:4 |
Page generated in 0.0017 seconds