The first topic of this thesis presents a one-time programmable (OTP) ROM using a standard logic CMOS process. A high voltage is applied to the gate-oxide to breakdown the MOS in the ROM-cell. It results in a low resistance compared to that of unprogrammed cells. Therefore, we can realize an OTP ROM with this characteristic on a CMOS logic ASIC or SOC.
The second topic is a DDFS (Direct Digital Frequency Synthesizer) implementation. A straight-line approximation algorithm for sinusoid with compensation is adopted in the proposed DDFS such that the accuracy could be maintained and the cost is reduced. Most important of all, the proposed CMOS OTP ROM is employed as the sinusoidal look-up ROM table to simplify the ROM fabrication without any additional process step.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0716107-111337 |
| Date | 16 July 2007 |
| Creators | Jhuang, Guo-Lin |
| Contributors | Tzyy-Sheng Horng, Jia-Jin chen, Chua-Chih Wang, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716107-111337 |
| Rights | not_available, Copyright information available at source archive |
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