1 
VLSI Design and Implementation of A Platch Ndrive SRAM and Digital Frequency SynthesizersTseng, YihLong 27 September 2005 (has links)
Highspeed systems and mobile systems are the main trends of the IC developments in these years. A highspeed system must have highspeed calculation units, such as CPUs and DSPs, and high speed memories.
A high speed Platch Ndrive 4T SRAM cell using the dual
threshold voltage transistors is proposed in thesis. The highVth transistors are used to construct data storage latches, and the lowVth transistors are used to improve driving capability and speed. Meanwhile, a DLLbased
frequency multiplier which can provide the high speed clocks in the high speed SRAMs is also proposed. Besides a current mirror, the rest of the DLLbased frequency multiplier is a purely digital logic, which in turn
eliminates the noise prone problem.
Modern mobile systems usually demand a fast frequency hopping and a precise modulation. We introduce a novel method utilizing the trigonometric quadruple angle formula to reduce the spurious tones of the DDFSs, which can serve as a cosine function generator for the mobile systems. The proposed DDFS has a very high resolution. The fast frequency hopping can be achieved by the DDFS and the frequency multiplier serving a local oscillator.

2 
DifferentialtoSingle Voltage Buffer Amplifier for DDFS and Wireless Duplex Modulation Circuit Using A Single CoilYao, Tuoyu 28 August 2009 (has links)
The thesis is composed of two topics: the differential to single voltage buffer amplifier used in DDFS designs and a wireless duplex modulation circuit with a single coil for bioimplants.
A voltage buffer implemented in 2P4M 0.35 £gm CMOS process, which is addressed in first part of this thesis, can amplify the small sinusoid outputs from DDFS (direct digital frequency synthesizer, DDFS), while convert the differential output into a singleend output. Not only can it amplify signal by a predefined multiple, but also reduce the common mode noise coupled from DDFS.
A wireless duplex modulation circuit using a single coil for biomedical implantable systems is disclosed in the second part of this thesis. It enables full duplex communication between the external controller and the implants at same time by a wireless a RF transmission interface. Since the proposed duplex design employs a single coil, the volume of the implanted device is drastically reduced.

3 
A High Speed Phase Adjustable ROMless DDFS and LowPower SRAM DesignLin, WunJi 10 July 2004 (has links)
This thesis includes two topics. The first topic is a high speed phase adjustable ROMless DDFS (Direct Digital Frequency Synthesizer). The second one is a lowpower SRAM design.
The high speed phase adjustable ROMless DDFS employs trigonometric quadruple angle formula with the adjustability of phase and frequency. Neither any scaling tables nor error correction tables are required. In order to meet demands of general communication systems, the ROMless DDFS is aimed at generating the frequencies for IQ channels. A pipelining design is adopted in our design to boost the frequency of the DDFS.
The lowpower SRAM uses a negative wordline scheme to reduce the leakage current of wordline controlled transistors (WCT). The leakage current increases with the high density of SRAM which might cause reading and writing errors. The negative wordline scheme not only reduces the leakage current as well as the power, but also makes the SRAM operate reliably during read and write cycles.

4 
A ROMless DDFS Using A Parabolic Polynomial Interpoltion Method with An Offset Adjustment and Fabrication of Silconbased OEIC Comprising Photodetector and Transimpedance AmplifierLee, ChiaChuan 14 July 2008 (has links)
This thesis includes two topics. The first topic is a ROMless DDFS (Direct Digital Frequency Synthesizer) using a parabolic polynomial interpolation method with an offset adjustment. The second one is the design and fabrication of a siliconbased OEIC(optoelectronic integrated circuit) comprising photodetectors and transimpedance amplifiers.
The ROMless DDFS employs a parabolic polynomial interpola?tion method with an offset adjustment, where an initial phase offset is added into parabolic polynomials. Besides, the pipelining architecture is adopted to improve the speed of the proposed DDFS.
The OEIC uses the hybrid integration technique to integrate the IIIV optoelectronic devices (photodetector) and CMOS integrated circuits (transimpedance amplifier) onto the same substrate (silicon substrate) by the wafer bounding technique. With the realization of the hybrid integration, the bandwidth degeneration resulted from the traditional wire bounding can be avoided.

5 
Ultra LowPower Direct Digital Frequency Synthesizer Using a Nonlinear DigitaltoAnalog Converter and an Error Compensation MechanismChen, JianTing 11 July 2007 (has links)
This thesis includes two topics. The first one is the architecture as well as the circuit implementation of an ultra lowpower direct digital frequency synthesizer (DDFS) based on the straight line approximation. The second one is the circuit implementation of the lowpower DDFS with an error compensation.
The proposed approximation technique replaces the conventional ROMbased phasetoamplitude conversion circuitry and the linear digitaltoanalog converter with a nonlinear digitaltoanalog converter (DAC) to realize a simple approximation of the sine function. Thus, the overall power dissipation as well as hardware complexity can be significantly reduced. Besides, by adding the error compensation, the spuriousfree dynamic range (SFDR) of the synthesized output signal can be raised drastically.

6 
An OTP ROM Using a Standard Logic CMOS Process and The Application In a DDFS ImplementationJhuang, GuoLin 16 July 2007 (has links)
The first topic of this thesis presents a onetime programmable (OTP) ROM using a standard logic CMOS process. A high voltage is applied to the gateoxide to breakdown the MOS in the ROMcell. It results in a low resistance compared to that of unprogrammed cells. Therefore, we can realize an OTP ROM with this characteristic on a CMOS logic ASIC or SOC.
The second topic is a DDFS (Direct Digital Frequency Synthesizer) implementation. A straightline approximation algorithm for sinusoid with compensation is adopted in the proposed DDFS such that the accuracy could be maintained and the cost is reduced. Most important of all, the proposed CMOS OTP ROM is employed as the sinusoidal lookup ROM table to simplify the ROM fabrication without any additional process step.

7 
Design and Implementation of the OFDM Demodulator for DVBT and the Random Number GeneratorHuang, Jianming 15 October 2008 (has links)
Digital video broadcasting for Terrestrial (DVBT) is one of the major standards for the fixed reception of digital television services, and the orthogonal frequency division multiplexing (OFDM) demodulator is a critical module of DVBT receivers. As the remarkable advace of the VLSI (very large scale integration) circuits, the SOC (systemonachip) of the DVBT receiver is an inevitabel evolution. Considering the integration of the mixedsignal circuits, the issues ot beat could be the frequency synthesis and the calibration of the mixedsignal circuits. Hence, this thesis proposes an OFDM demodulator and discusses the design issues emerged from the SOC integration.
The proposed OFDM demodulator is composed of four blocks: time synchronization, frequency synchronization, 2K/8K mode FFT (fast Fourier transform), and channel estimation. The demodulator utilizes the pilot signals embeded in OFDM symbols to estimate the frequency offset and the channel response. Besides, the demodulator use the cyclic prefix of an OFDM symbol to find the correct starting position of an OFDM symbol, and consequently the payload data of an OFDM symbol can be transmitted to the 2K/8K FFT for further processing.
As the demand for a low noise frequency signal, we propose a direct digital frequency synthesizer (DDFS) based on the quadruple angle approximation. According to the proposed trigonometric 2ndorder quadruple angle approximation, the DDFS can produce a highresolution and lowphase noise digital sinusoid without any ROM (read only memory).
The digital calibration is an effective scheme to prevent ADCs (analogtodigital converter) from the interference of noise. A random number generator (RNG) is an essential component for the calibration circuitry. However, the realization of the RNG is an important but long ignored issue. This thesis proposes a RNG based on a chaotic system wherein the coefficients of the system is dynamically changed to attain an ideal random bit stream with flat power spectrum density.

8 
Direct Digital Frequency Synthesis in FieldProgrammable Gate Arrays / Digital Frekvenssyntes för FPGAerKällström, Petter January 2010 (has links)
<p>This thesis is about creation of a Matlab program that suggests and automatically generates a Phase to Sine Amplitude Converter (PSAC) in the hardware language VHDL, suitable for Direct Digital Frequency Synthesis (DDFS). Main hardware target is Field Programmable Gate Arrays (FPGAs).</p><p>Focus in this report is how an FPGA works, different methods for sine amplitude generation and their signal qualities vs the hardware resources they use.</p> / <p>Detta exjobb handlar om att skapa ett Matlabprogram som föreslår och implementerar en sinusgenerator i hårdvaruspråket VHDL, avsedd för digital frekvenssyntes (DDFS). Ämnad hårdvara för implementeringen är en fältprogrammerbar grindmatris (FPGA).</p><p>Fokus i denna rapport ligger på hur en FPGA är uppbyggd, olika metoder för sinusgenerering och vilka kvaliteter på sinusvågen de ger och vilka resurser i hårdvaran de använder.</p>

9 
ROMless DDFS Using NonEqual Division Parabolic Polynomial Interpolation Method and FrequencyShift Readout Circuit for Rapid IgE Measurement SystemChen, YunChi 07 July 2012 (has links)
This thesis consists of two topics. A frequencyshift readout circuit is integrated for the rapid IgE measurement biomedical system in the first half. Secondly, we present a ROMless DDFS (direct digital frequency synthesis) using a nonequal division parabolic polynomial interpolation method, which is used as the frequency generator in the measurement system.
The first topic investigates the IgE concentration measurement system and realizes the readout circuit using TSMC 1P6M 0.18 £gm CMOS technology. We integrate the flexural plate wave (FPW) sensor chips and an ASIC comprising control block, digital to analog convertor (DAC), OTAC oscillators, amplifiers, peak detectors, registers, and a subtractor. By taking advantages of the characteristics that the central frequencies of the loaded FPW sensors will be shifted, sine waves with various frequencies are generated and swept through one pair of FPW sensors. The frequency difference of these sensors is then readout to get concentration by lookup table.
The second topic investigates the division method of a quarter sine wave to improve the spurious free dynamic range (SFDR) and realizes a ROMless DDFS which is used as the frequency generator in the mentioned IgE measurement system. The proposed nonequal division parabolic polynomial interpolation method will generate a complete sine wave by a quarter of a sine digital signal owing to the symmetry. We combine the quasilinear interpolation and an offset adjustment to derive the quarter sine wave digital signals. The proposed method not only reduces the absolute error between ideal sine wave and generated sine wave, it also improves SFDR.

10 
Design and Implementation of Onetime Implantable Spinal Cord Stimulation SystemHsu, ChiaHao 07 July 2012 (has links)
A prototype of a onetime implantable spinal cord stimulation (SCS) system is presented in this thesis. A pair of inductive coils is used to achieve wireless power transmission and bidirectional communication. A rechargeable Liion battery is used to extend the lifetime of the implanted SCS device. Therefore, the number of the battery replacement surgery could be reduced such that onetime implantation is feasible. Besides, the proposed system on chip (SOC) controller and many discretes are integrated on a printed circuit board (PCB). The size of the proposed SCS device is competitive compared to the currently commercial products. The proposed SOC controller adopts a dual supply voltage scheme to reduce power consumption.
The proposed SCS system employs an amplitudeshift keying (ASK) technique to carry out the data modulation and power transmission. One of the critical factors to affect efficiency of ASKbased wireless power transmission is the oscillating frequency accuracy. A ROMless direct digital frequency synthesizer (DDFS) is presented in this thesis to fulfill such a high accuracy demand.
Since the supply voltages of the discretes are diversified on a system PCB, many level converters are needed to translate different signal output voltage levels. To resolve above problem, the chip, then, must be redesigned to meet the various voltage level requirement, or added level convertors among the SOC and the discretes. Obviously, it will cause a lot of cost. A widerange I/O buffer, thus, is proposed to resolve the compatibility problem caused by different supply voltages of discretes.

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