This thesis includes two topics. The first one is the architecture as well as the circuit implementation of an ultra low-power direct digital frequency synthesizer (DDFS) based on the straight line approximation. The second one is the circuit implementation of the low-power DDFS with an error compensation. The proposed approximation technique replaces the conventional ROM-based phase-to-amplitude conversion circuitry and the linear digital-to-analog converter with a nonlinear digital-to-analog converter (DAC) to realize a simple approximation of the sine function. Thus, the overall power dissipation as well as hardware complexity can be significantly reduced. Besides, by adding the error compensation, the spurious-free dynamic range (SFDR) of the synthesized output signal can be raised drastically.

In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and their advantages and disadvantages. We have mainly focused on current-steering digital-to-analog design for achieving high speed and high performance. The current-steering DAC is designed using binary weighted architecture. The benefits of this architecture is that it occupies less area, consumes less power and the number of control signals required are very less. The requirements for high speed and high performance DAC are discussed in detail. The circuit is implemented in a state-of-the-art 65 nm process, with a supply voltage of 1.2 V and at a sampling speed of 2 GHz. The resolution of the DAC is 8-bits. The design of 8-bit current-steering DAC converts 8 most significant bits (MSBs) into their binary weighted equivalent, which controls 256 unit current sources. The performance of the DAC is measured using the static and dynamic  parameters. In communication applications the static performance measures such as INL and DNL are not of utmost importance. In this work, we have mainly concentrated on the dynamic performance characteristics like SNR (Signal to Noise Ratio) and SFDR (Spurious Free Dynamic Range). For measuring the dynamic parameters, frequency domain analysis is a better choice. Also, we have discussed how the pole-zero analysis can be used to arrive at the dynamic performance metrics of a unit element of the DAC at higher frequencies. Different methods were discussed here to show the effects of poles and zeroes on the output impedance of a unit element at higher frequencies, for example, by hand calculation, using Mathematica and by using cadence. After extensive literature studies, we have implemented a technique in cadence, to increase the output impedance at higher frequencies. This technique is called as “complimentary current solution technique”. This technique will improve the output impedance and SFDR compared to the normal unit element design. Our technique contains mostly analog building blocks, like, current mirrors, biasing scheme and switching scheme and few digital blocks like D-ff (D-flip flop). The whole system is simulated and verified in MATLAB. Dynamic performances of the DAC such as SNR and SFDR are found with the help of MATLAB.

In this work a low voltage and highly linear current-mode current to delay (CTD) converter is presented. The proposed current to delay converter has the improved linearity of about 23.5% when compared with a conventional–delay inverter over the input dynamic current range of 50µA. When used as front-end block in current-mode delay-mode analog to digital converter an 11-bit resolution is obtained. The design is implemented in TSMC 90 nm CMOS technology. Monte Carlo analysis and process corner analysis is performed on the proposed circuit to analyze the amount of mismatch that will degrade the performance of the circuit in a system level. A Process, Voltage, and Temperature (PVT) variation insensitive circuit is used to bias the designed CTD converter to obtain 57% reduction of variation when compared with the simple current mode biasing technique.

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier's voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses.

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Submitted by JORGE ESTEBAN BLANCO RODRIGUEZ null (lobogris87@msn.com) on 2016-06-01T14:53:04Z No. of bitstreams: 1 Jorge Esteban Blanco Rodriguez.pdf: 3365866 bytes, checksum: edf247c26e3f44cc20ef44607e947f0e (MD5) / Rejected by Ana Paula Grisoto (grisotoana@reitoria.unesp.br), reason: Solicitamos que realize uma nova submissão seguindo as orientações abaixo: O mês informado na capa do documento está diferente da data de defesa que consta na folha de aprovação. Corrija esta informação no arquivo PDF e realize uma nova submissão contendo o arquivo correto. Agradecemos a compreensão. on 2016-06-02T13:45:11Z (GMT) / Submitted by JORGE ESTEBAN BLANCO RODRIGUEZ null (lobogris87@msn.com) on 2016-06-02T14:37:35Z No. of bitstreams: 1 Jorge Esteban Blanco Rodriguez 30-03-2016.pdf: 2668564 bytes, checksum: 75234917c13bea3285297fb6aeb7f0ec (MD5) / Approved for entry into archive by Ana Paula Grisoto (grisotoana@reitoria.unesp.br) on 2016-06-02T16:43:57Z (GMT) No. of bitstreams: 1 blancorodriguez_je_me_ilha.pdf: 2668564 bytes, checksum: 75234917c13bea3285297fb6aeb7f0ec (MD5) / Made available in DSpace on 2016-06-02T16:43:57Z (GMT). No. of bitstreams: 1 blancorodriguez_je_me_ilha.pdf: 2668564 bytes, checksum: 75234917c13bea3285297fb6aeb7f0ec (MD5) Previous issue date: 2016-03-30 / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Implementou-se um estimulador elétrico funcional para uso na reabilitação de pacientes hígidos e paraplégicos e que não necessita de alimentação simétrica. O equipamento é constituído por dois estágios, o formador de onda, no qual se define os parâmetros do sinal de estimulação, e o de potência. No formador de onda foi utilizado uma placa Raspberry pi e uma interface de usuário, desenvolvida em Python. O estágio de potência é composto por um espelho de corrente que possibilita a utilização de transistores não casados, e uma estrutura em ponte H, para formar o sinal de eletroestimulação bifásico, sem a necessidade de fonte simétrica, diminuindo assim pela metade a diferença de potencial aplicada na alimentação do circuito. Com o estimulador implementado gerou-se correntes com forma de onda retangular, amplitude de até 120 mA e características adequadas para utilização na reabilitação dos membros inferiores e superiores de pacientes. / A functional electrical stimulator for use in the rehabilitation of paraplegic and healthy patients was implemented. It does not need symmetrical power supply. The equipment consists of two stages, the wave generator, which defines the stimulation signal parameters, and the power stage. In the wave generator we have used a Raspberry Pi board and a user interface, developed in Python. In the power stage we have used a current mirror which enables the use of unmarried transistors and a H-bridge circuit to generate a biphasic signal. With the implemented stimulator, currents with rectangular waveform, range of up to 120 mA, and suitable characteristics for using in rehabilitation of the lower and upper limbs of patients were generated.

Orientador: Aparecido Augusto de Carvalho / Resumo: Implementou-se um estimulador elétrico funcional para uso na reabilitação de pacientes hígidos e paraplégicos e que não necessita de alimentação simétrica. O equipamento é constituído por dois estágios, o formador de onda, no qual se define os parâmetros do sinal de estimulação, e o de potência. No formador de onda foi utilizado uma placa Raspberry pi e uma interface de usuário, desenvolvida em Python. O estágio de potência é composto por um espelho de corrente que possibilita a utilização de transistores não casados, e uma estrutura em ponte H, para formar o sinal de eletroestimulação bifásico, sem a necessidade de fonte simétrica, diminuindo assim pela metade a diferença de potencial aplicada na alimentação do circuito. Com o estimulador implementado gerou-se correntes com forma de onda retangular, amplitude de até 120 mA e características adequadas para utilização na reabilitação dos membros inferiores e superiores de pacientes. / Abstract: A functional electrical stimulator for use in the rehabilitation of paraplegic and healthy patients was implemented. It does not need symmetrical power supply. The equipment consists of two stages, the wave generator, which defines the stimulation signal parameters, and the power stage. In the wave generator we have used a Raspberry Pi board and a user interface, developed in Python. In the power stage we have used a current mirror which enables the use of unmarried transistors and a H-bridge circuit to generate a biphasic signal. With the implemented stimulator, currents with rectangular waveform, range of up to 120 mA, and suitable characteristics for using in rehabilitation of the lower and upper limbs of patients were generated. / Mestre

Oscillators are components providing clock signals. They are widely required by low-cost on-chip applications, such as biometric sensors and SoCs. As part of a sensor, a relaxation oscillator is implemented to provide a clock reference. Limited by the sensor application, a clock reference outside the sensor is not desired. An RC implementation of the oscillator has a balanced accuracy performance with low-cost advantage. Hence an RC relaxation oscillator is chosen to provide the clock inside the sensor. This thesis proposes a current mode relaxation oscillator to achieve low frequency standard deviation across different supplies, temperatures and process corners. A comparison between a given relaxation oscillator and the proposed design is made as well. All oscillators in this thesis use 0.18 μm technology and 1.8 V nominal supply. The proposed oscillator manages to achieve a frequency standard deviation across all PVT variations less than ±6.5% at 78.4 MHz output frequency with a power dissipation of 461.2 μW. The layout of the oscillator's core area takes up 0.003 mm2.

The present work deals with issues of a design of operational transconductance amplifier in technology CMOS AMIS 0,7 um. The aim of the work is to design a accurate operational amplifier with a low input differential voltage.

The topic of the master´s thesis are voltage and current reference sources. There is detailed description of current and voltage references, which are basic building blocks of many analog circuits, in the theoretical part. Next part of the master´s thesis is the design of a voltage reference source, the design of a voltage reference generating two voltages and a current reference source. The correct function of all circuits have been verified using simulations, especially dependence of the output voltage or current on supply voltage or dependence of the output voltage or current when the ambient temperature is changed.