This thesis includes two topics. The first one is the architecture as well as the circuit implementation of an ultra low-power direct digital frequency synthesizer (DDFS) based on the straight line approximation. The second one is the circuit implementation of the low-power DDFS with an error compensation. The proposed approximation technique replaces the conventional ROM-based phase-to-amplitude conversion circuitry and the linear digital-to-analog converter with a nonlinear digital-to-analog converter (DAC) to realize a simple approximation of the sine function. Thus, the overall power dissipation as well as hardware complexity can be significantly reduced. Besides, by adding the error compensation, the spurious-free dynamic range (SFDR) of the synthesized output signal can be raised drastically.