The thesis is composed of two topics : a fully bidirectional mixed-voltage-tolerant I/O buffer using a clamping dynamic gate bias generator and a wide range fully bidirectional mixed-voltage-tolerant I/O buffer with a calibration function. The first topic, a mixed-voltage-tolerant I/O buffer implemented in 2P4M 0.35 £gm CMOS process, comprises a low-power bias circuit with clamping transistors in a feedback loop, a power supply level detector circuit, a voltage level converter circuit, a logic switch circuit, a dynamic driving detector circuit, and a clamping dynamic gate bias generator. The proposed design can transmit and receive digital signals with voltage levels of 5/3.3/1.8 V without any gate-oxide overstress and leakage current path in different voltage interface applications. The second topic, a 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage-tolerant I/O buffer carried out in 2P4M 0.35 £gm CMOS technology, contains a dynamic gate bias generator to provide appropri¬ate gate voltages for the output stage composed of stacked PMOS and stacked NMOS, an I/O buffer which can transmit the signal with a higher voltage level (VDDH), a floating N-well circuit to remove the body effect at the output PMOS, and a dynamic driving detector to balance the turn-on voltages for the pull-up PMOS and pull-down NMOS in the output stage. The duty cycle of the output signal of the proposed I/O buffer can then be equalized even if the output stage power supply is biased at a low voltage. In order to adapt to wide range input voltage applications, a logic calibration circuit is added in the input buffer.

A prototype of a one-time implantable spinal cord stimulation (SCS) system is presented in this thesis. A pair of inductive coils is used to achieve wireless power transmission and bidirectional communication. A rechargeable Li-ion battery is used to extend the lifetime of the implanted SCS device. Therefore, the number of the battery replacement surgery could be reduced such that one-time implantation is feasible. Besides, the proposed system on chip (SOC) controller and many discretes are integrated on a printed circuit board (PCB). The size of the proposed SCS device is competitive compared to the currently commercial products. The proposed SOC controller adopts a dual supply voltage scheme to reduce power consumption. The proposed SCS system employs an amplitude-shift keying (ASK) technique to carry out the data modulation and power transmission. One of the critical factors to affect efficiency of ASK-based wireless power transmission is the oscillating frequency accuracy. A ROM-less direct digital frequency synthesizer (DDFS) is presented in this thesis to fulfill such a high accuracy demand. Since the supply voltages of the discretes are diversified on a system PCB, many level converters are needed to translate different signal output voltage levels. To resolve above problem, the chip, then, must be redesigned to meet the various voltage level requirement, or added level convertors among the SOC and the discretes. Obviously, it will cause a lot of cost. A wide-range I/O buffer, thus, is proposed to resolve the compatibility problem caused by different supply voltages of discretes.

This thesis is composed of two parts : a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, and a 2¡ÑVDD output buffer with process and temperature compensation. In the first topic, a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, which is able to tolerate 3¡ÑVDD using stacking transistors in the output stage, is proposed. These transistors are biased by corresponding voltage levels which are generated by a dynamic gate bias generator and a floating N-well circuit when transmitting or receiving signals. In order to prevent the input stage transistors from gate-oxide overstress, an NMOS clamping technique is used to block high input voltages. This design can receive and transmit 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5.0 V) signals, which has been implemented using TSMC 1P6M 0.18 £gm CMOS process. The second topic shows a 2¡ÑVDD output buffer with process and temperature compensation using 1P6M 0.18 £gm CMOS process. In this design, a novel process and temperature variation detector is proposed to detect the corners of NMOS and PMOS, respectively. The driving capability of the output stage is enhanced at those corners with low output currents. By contrast, the driving currents is reduced at those corners with high output currents to reduce the variation of output slew rate.

This thesis is composed of two parts: a 3¡ÑVDD mixed-voltage-tolerant I/O buffer with 1¡ÑVDD CMOS standard device, and a PVT detector for 2¡ÑVDD output buffer with slew-rate compensation. In the first topic, a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, which has been implemented using a typical TSMC 0.18 £gm CMOS process, is proposed with a Dynamic gate bias voltage generator to provide appropriate gate drives for the stacked output stage. Besides, a Gate-tracking circuit and a Floating N-well technique are adopted to prevent 1¡ÑVDD device from gate-oxide overstress problems and leakage currents. The maximum data rate is simulated to be 166/166/166/100/80 MHz when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, respectively, given an equivalent probe capacitive load of 10pF. The second topic is a process, voltage, and temperature¡]PVT¡^detector for 2¡ÑVDD output buffer with slew-rate compensation. The threshold voltage¡]Vth¡^ of PMOSs and NMOSs varying with process variation could be detected, respectively. In addition, the voltage and temperature variations could be monitored, respectively, by detecting different charging and discharging times of delay buffers at each PVT corner. By adjusting output currents, the slew rate of output signals could be compensated over 24¢H. Moreover, the maximum data rate with compensation is 133 MHz in contrast with 100 MHz without compensation when VDDIO ¡× 1.8 V, in transmitting mode.