This thesis is composed of two designs: a PT (process, temperature) detector for 2¡ÑVDD output buffer with slew rate compensation, and a slew rate self-adjusting 2¡ÑVDD output buffer with PVT compensation. In the first topic, a PT detector for 2¡ÑVDD output buffer with slew-rate compensa-tion is proposed. The driving current of 2¡ÑVDD output stages varies provided that the process and temperature conditions are different. For example, the driving current of 2¡ÑVDD output stage will be low at poor PVT corners. By contrast, the driving current will be high at good PVT corners. The process corner and temperature of NMOS and PMOS should be detected by threshold voltage variation thereof, respectively, such that the slew rate compensation is feasible. The proposed sensors will carry out the PT de-tection and compensate the driving current based on the detected corner, such that the slew rate variation of the output stage will be reduced. The second topic is a slew rate self-adjusting 2¡ÑVDD output buffer with PVT compensation. An NMOS and PMOS process detector is proposed to detect the process corners of NMOS and PMOS, respectively, while the voltage and temperature sensor is proposed to detect the voltage and temperature variations by body effect.

This thesis is composed of two parts : a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, and a 2¡ÑVDD output buffer with process and temperature compensation. In the first topic, a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, which is able to tolerate 3¡ÑVDD using stacking transistors in the output stage, is proposed. These transistors are biased by corresponding voltage levels which are generated by a dynamic gate bias generator and a floating N-well circuit when transmitting or receiving signals. In order to prevent the input stage transistors from gate-oxide overstress, an NMOS clamping technique is used to block high input voltages. This design can receive and transmit 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5.0 V) signals, which has been implemented using TSMC 1P6M 0.18 £gm CMOS process. The second topic shows a 2¡ÑVDD output buffer with process and temperature compensation using 1P6M 0.18 £gm CMOS process. In this design, a novel process and temperature variation detector is proposed to detect the corners of NMOS and PMOS, respectively. The driving capability of the output stage is enhanced at those corners with low output currents. By contrast, the driving currents is reduced at those corners with high output currents to reduce the variation of output slew rate.