Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers. The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. ¢Ï synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators.

Since the invention of SRAM (Static Random Access Memory), many improvements have been proposed. The major targets are speed, area, and power consumption. The evolution of the CMOS process technology makes it possible to implement SRAM by using dual threshold voltage transistors. Hence, we will use TSMC (Taiwan Semiconductor Manufacturing Company) 0.25 $mu$m 1P5M CMOS process to realize the dual threshold voltage SRAM in this thesis. In order to reduce SRAM internal power consumption, we also propose quenchers to suppress unwanted oscillation between bit lines. In addition, several types of BIST (Build In Self Test) comparators are also proposed to test the mentioned SRAM. After detailed simulations, the proposed comparators possess impressive results in high fan-in, low transistor count, and high speed. The proposed SRAM and BIST comparators are fabricated by the CMOS process provided by National Science Council Chip Implementation Center (CIC). The measurements of the chips are fully corrected to meet the design goals.

Chalcogenide phase change (PC) materials can be reversibly transformed between the high resistivity (~ 1 Ω∙m) amorphous state (OFF-state) and low resistivity (~ 10-6 Ω∙m) crystalline state (ON-state) thermally, both are stable at the room temperature. This makes them well suited as reconfigurable RF switches and non-volatile memories. This work will present the understandings of two key characteristics of PC materials, the crystallization dynamics and the threshold voltage (Vth), as they determine performance limitations in these applications. Crystallization dynamics describe the correlations of the states, temperature and time; the Vth is the trigger of the threshold switching which leads to the “break down” of PC materials from OFF-state to ON-state. The four-terminal indirectly-heated RF switches with high cut-off frequency (> 5 THz) has advantages over other technologies but its programming power (~ 1.5 W) is yet to be reduced. Measuring the maximum allowed RESET quench time in the crystallization dynamics is critical for designing low power switches. As a major contribution, this work provides a universal methodology for accurate heater thermometry and in-situ crystallization measurements for this study. On the other hand, understanding the Vth is essential for high power handling applications as it determines the maximum power that an OFF-state switch can withstand without being spontaneously turned on. This work will discuss new observations and learnings from Vth measurements including the geometry dependent Vth variations which provide insights into the threshold switching mechanism. Unlike RF switches, faster crystallization is desired for memories to improve the write speed. The non-Arrhenius crystallization needs to be explored to achieve short crystallization time (< 10 ns) at high temperature (> 700 K). As another major contribution, this work will present a nano-scale (~ 100 nm) high-speed (thermal time constant < 5 ns) PC device for assessing the crystallization time in this regime, and provide a comprehensive learning for the crystallization dynamics from 300 K to 1000 K by developing a unified framework based on the fragility model and growth-dominated crystallization. This can be used to accurately simulate the crystallization process for any device geometry and estimate the RF switches power and Vth.

The objective of this research is to comprehensively compare bulk accumulation and inversion MOSFETs, and find application areas where each is superior.Short channel effect (SCE) models for accumulation and inversion MOSFETs are derived that accurately predict threshold voltage, subthreshold swing, and subthreshold current. A source/drain junction depth dependent characteristic length is derived that can be used to rapidly assess the impact of junction depth scaling on minimum channel length. A fast circuit simulation methodology is developed that uses physically based I-V models to simulate inversion and accumulation MOSFET inverter chains, and is found to be accurate over a wide range of supply voltages. The simulation methodology can be used for rapid technology optimization, and performance prediction. Design guidelines are proposed for accumulation MOSFET design; the guidelines result in a low process sensitivity, low SCE, and a subthreshold current less than the allowable limit. The relative performance advantage of accumulation/inversion MOSFETs is gate-technology dependent. In critical comparisons, on-current is evaluated by means of a full band Monte Carlo device simulation. Gate-leakage, and band-to-band tunneling leakage at the drain-substrate region are included in the performance analysis. For mid-bandgap metal gate, accumulation MOSFETs perform better than inversion MOSFETs for hi-performance (HiP) and low-operating power (LOP) applications. For tunable metal gate technology, inversion MOSFETs always perform better than accumulation MOSFETs. For dual poly technology, accumulation MOSFETs perform better than inversion MOSFETs for low standby power (LSTP) applications. A comprehensive scaling analysis has been performed on accumulation and inversion MOSFETs using both SCE models and 2-D simulations. Results show that accumulation MOSFETs can scale better than inversion MOSFETs for mid-bandgap metal gate HiP, and LOP applications; and poly gate LSTP applications.

This thesis is composed of two designs: a PT (process, temperature) detector for 2¡ÑVDD output buffer with slew rate compensation, and a slew rate self-adjusting 2¡ÑVDD output buffer with PVT compensation. In the first topic, a PT detector for 2¡ÑVDD output buffer with slew-rate compensa-tion is proposed. The driving current of 2¡ÑVDD output stages varies provided that the process and temperature conditions are different. For example, the driving current of 2¡ÑVDD output stage will be low at poor PVT corners. By contrast, the driving current will be high at good PVT corners. The process corner and temperature of NMOS and PMOS should be detected by threshold voltage variation thereof, respectively, such that the slew rate compensation is feasible. The proposed sensors will carry out the PT de-tection and compensate the driving current based on the detected corner, such that the slew rate variation of the output stage will be reduced. The second topic is a slew rate self-adjusting 2¡ÑVDD output buffer with PVT compensation. An NMOS and PMOS process detector is proposed to detect the process corners of NMOS and PMOS, respectively, while the voltage and temperature sensor is proposed to detect the voltage and temperature variations by body effect.

This thesis includes two topics. The first topic is a CMOS SRAM using dynamic threshold voltage wordline-transistors, which is focused on high speed applications. The second one is a high voltage generator for FLASH memories. The generated high voltages are applied to the wordline controlled transistors during access and verification operations. By taking advantage of the large current provided by low Vth and low leakage current provided by high Vth, a CMOS SRAM using dynamic threshold voltage wordline transistors is presented. The design of a 4-Kb SRAM is measured to possess a 2.2 ns access time, and consume 43.6 mW in the standby mode. The highest operating clock rate is estimated to be 667 MHz. A high voltage generator using 4 clocks with two phases is presented to provide a high voltage supply required by FLASH memories during programming mode and erase mode operations. The circuit is implemented by TSMC 0.25um 1P5M CMOS process. It can provide as high as +11.7 V and -11.6 V by given VDD=2.5 V.

Abstract The electrical pitting often occurs at the bearing of the ro-tating machinery due to the actions of the shaft voltage and the shaft current resulting in the arcing effect on the lubricated surface and causing the bearing failure. Since the mechanism of the electrical pitting cannot be microscopically observed in process, it is difficult to prevent the bearing damage. Hence, this study uses a static electrical pitting tester with sub -micrometer accuracy to experimentally investigate the effects of supply voltage, supply current, oil film thickness, and ad-ditive on the threshold condition of electrical pitting under the conventional bearing material pairs. Moreover, according to the SEM micrograph and EDS analysis, the mechanism of the pitted surfaces is investigated. According to the experimental results and the surface ob-servations of steel/steel pair using a paraffin base oil, three electrical pitting regimes are found under the influences of shaft voltage and oil film thickness, namely, pitting, transition, and no-pitting regimes. In the electrical pitting regime, the interface voltage, interface impedance, and interface power increases slightly with increasing oil film thickness at a certain supply current. However, the interface voltage and interface power increases with increasing supply current, and the inter-face impedance decreases with increasing supply current at a certain film thickness. Furthermore, the pitting area versus the interface power relationship is a cubic function. According to the experimental results and the surface ob-servations of babbitt alloy/steel pair using a paraffin base oil, two electrical pitting regimes are found under the influences of shaft voltage, oil film thickness, and melting point of material, namely, pitting and no-pitting regimes. The mechanism of electrical pitting on the babbitt alloy surface is significantly influenced by the interface power and the oil film thickness. At the smaller oil film thickness, the eroded surface of babbitt alloy exhibits a concave crater with a few micro-porosity in the vicinity of center region with a plateau on its surrounding, especially at high supply current. The polished track can be observed at the plateau. A large amount of tin element trans-fers to the steel ball surface because the molten tin contacts the ball. At the higher oil film thickness, only a little amount of metal element transfers to each other. The major pitting area of the babbitt alloy is caused at the initial stage of the arc dis-charge. With increasing arc discharge time, the pitting area increases slightly, and finally reaches a saturated value. According to the experimental results and the surface ob-servations of babbitt alloy/steel pair using an additive of MoS2 in a paraffin base oil, two electrical pitting regimes are found under the influences of shaft voltage, oil film thickness, and particle concentration of additive, namely, pitting and no-pitting regimes. The area of pitting regime increases with increasing additive concentration and supply current. Fur-thermore, the ratio of pitting area to the interface power in-creases with increasing additive concentration and supply current at the oil film thickness smaller than 6 mm. However, this ratio increases rapidly to about 10 times with increasing additive concentration and supply current as the oil film thickness increases from 6 mm to 10 mm. This results from the molten plateau that directly connects two specimens, and the interface power is mainly consumed at the heating of the pla-teau and the interfacial materials. According to the above re-sults, the growth model of the plateau on the pitting surface is proposed at the lubricated condition using an additive of MoS2 in paraffin base oil.

Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap. / A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.

Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap. / A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.

Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap. / A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.