The thesis is composed of two topics : a fully bidirectional mixed-voltage-tolerant I/O buffer using a clamping dynamic gate bias generator and a wide range fully bidirectional mixed-voltage-tolerant I/O buffer with a calibration function. The first topic, a mixed-voltage-tolerant I/O buffer implemented in 2P4M 0.35 £gm CMOS process, comprises a low-power bias circuit with clamping transistors in a feedback loop, a power supply level detector circuit, a voltage level converter circuit, a logic switch circuit, a dynamic driving detector circuit, and a clamping dynamic gate bias generator. The proposed design can transmit and receive digital signals with voltage levels of 5/3.3/1.8 V without any gate-oxide overstress and leakage current path in different voltage interface applications. The second topic, a 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage-tolerant I/O buffer carried out in 2P4M 0.35 £gm CMOS technology, contains a dynamic gate bias generator to provide appropri¬ate gate voltages for the output stage composed of stacked PMOS and stacked NMOS, an I/O buffer which can transmit the signal with a higher voltage level (VDDH), a floating N-well circuit to remove the body effect at the output PMOS, and a dynamic driving detector to balance the turn-on voltages for the pull-up PMOS and pull-down NMOS in the output stage. The duty cycle of the output signal of the proposed I/O buffer can then be equalized even if the output stage power supply is biased at a low voltage. In order to adapt to wide range input voltage applications, a logic calibration circuit is added in the input buffer.

The first topic of this thesis proposes a 10-bit, 30 Msample/s pipeline analog-to-digital converter (ADC) suitable for digital video broadcasting over handheld (DVB-H) systems. The ADC is based on the 1.5-bit-per-stage pipeline architecture. The proposed design is implement- ed by 0.18 um CMOS technology. The input range is 2 V peak-to-peak differential signals, and the post-layout simulation result shows that the spurious-free dynamic range (SFDR) is 57.85 dBc with a full-scale sinusoidal input at 700 KHz. The maximum power consumption is 37 mW given a 3.3 V power supply. The core area is 0.27 mm2. The second topic is to propose a fully mixed-voltage-tolerant I/O cell implemented using typical CMOS 2P4M 0.35 um process. Unlike traditional mixed-voltage-tolerant I/O cell, the proposed design can transmit and receive the digital signals with voltage levels of 5/3.3/1.8 V. By using stacked PMOS and stacked NMOS at the output stage and a voltage level converter providing appropriate control voltages for the gates of the stacked PMOS, the gate-oxide overstress and hot-carrier degradation are avoided. Moreover, gate-tracking and floating N-well circuits are used to remove the undesirable leakage current paths. The maximum transmitting speed of the proposed I/O cell is 103/120/84 Mbps for the supply voltage of I/O cell at 5/3.3/1.8 V, respectively, given the load of 20 pF.

In this thesis, we propose a personal gateway for wireless body area network(WBAN). By using wireless communication and a proper WBAN topology, patients¡¦ physiological signal could be recorded without restricting their mobility. Moreover, integration of several kinds of signals from different sensor nodes in one data platform, personal gateway (PG), can reduce the redundant hardware of individual links as well as the complexity of WBAN. A device for long-term bladder urine pressure measurement is designed as a sensor node of PG. Not only is the design cost reduced, but also the reliability is enhanced by using a 1-atm canceling sensing IA (instrumentation amplifier). Because the urine pressure inside the bladder does not vary drastically, both the sleeping and working modes are required to save the battery power for the long-term observation. To integrate circuits with different supply voltages in PG, a 0.9/1.2/1.8/2.5/3.3/5.0 V wide-range I/O buffer carried out using a typical CMOS process is designed. An input buffer with a logic calibration circuit is used for receiving a low voltage signal. A novel floating N-well circuit is employed to remove the body effect at the output PMOS. Moreover, a dynamic driving detector is included to equalize the turn-on voltages for the output PMOS and NMOS transistors. ZigBee is used as a communication channel in this thesis because of its features, including low power, low complexity, medium range, and medium data rate. The 868/915 MHz mode has lower cost and power consumption than those of 2.4 GHz mode, and the data rate is far enough for WBAN applications. Moreover, lower carrier frequency causes less unnecessary power absorbed by human tissue. Therefore, the ZigBee tranceiver with 868/915 MHz mode is explored. A low power all digital phase lock loop (ADPLL) using a controller which employs a binary frequency searching method is also proposed as a clock generator of PG. Glitch hazards and timing violations which occurred very often in prior ADPLLs are avoided by a novel control method and a new digital-controlled oscillator (DCO) with multiplexers. Besides, the feedback DCO is disabled half a cycle in every two cycles so as to reduce 25% of dynamic power theoretically.

This thesis is composed of two parts : a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, and a 2¡ÑVDD output buffer with process and temperature compensation. In the first topic, a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, which is able to tolerate 3¡ÑVDD using stacking transistors in the output stage, is proposed. These transistors are biased by corresponding voltage levels which are generated by a dynamic gate bias generator and a floating N-well circuit when transmitting or receiving signals. In order to prevent the input stage transistors from gate-oxide overstress, an NMOS clamping technique is used to block high input voltages. This design can receive and transmit 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5.0 V) signals, which has been implemented using TSMC 1P6M 0.18 £gm CMOS process. The second topic shows a 2¡ÑVDD output buffer with process and temperature compensation using 1P6M 0.18 £gm CMOS process. In this design, a novel process and temperature variation detector is proposed to detect the corners of NMOS and PMOS, respectively. The driving capability of the output stage is enhanced at those corners with low output currents. By contrast, the driving currents is reduced at those corners with high output currents to reduce the variation of output slew rate.

The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3¡ÑVDD wide range fully bidirectional mixed-voltage-tolerant I/O cell. The first topic discloses a mixed-voltage-tolerant I/O cell implemented using 2P4M 0.35 £gm CMOS process, which uses a low static power dynamic gate bias generator providing three different logic voltage levels to the output stage to avoid gate oxide reliability and leakage current. The design also reveals a new output stage circuit, which enhances the output current to resolve the poor driving capability caused by the slow mobility and body effect of the stacked PMOS. The second topic shows a sub-3¡ÑVDD wide range fully bidirectional mixed-voltage-tolerant I/O cell using 1P6M 0.18 £gm CMOS process, which employs a new dynamic gate bias generator and a PAD voltage detector to provide appropriate gate biases. The design includes a new gate tracking circuit and a floating N-well circuit to avoid gate oxide reliability and leakage current, which relaxes the body effect at the output PMOS.

This thesis is composed of two parts: a 3¡ÑVDD mixed-voltage-tolerant I/O buffer with 1¡ÑVDD CMOS standard device, and a PVT detector for 2¡ÑVDD output buffer with slew-rate compensation. In the first topic, a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, which has been implemented using a typical TSMC 0.18 £gm CMOS process, is proposed with a Dynamic gate bias voltage generator to provide appropriate gate drives for the stacked output stage. Besides, a Gate-tracking circuit and a Floating N-well technique are adopted to prevent 1¡ÑVDD device from gate-oxide overstress problems and leakage currents. The maximum data rate is simulated to be 166/166/166/100/80 MHz when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, respectively, given an equivalent probe capacitive load of 10pF. The second topic is a process, voltage, and temperature¡]PVT¡^detector for 2¡ÑVDD output buffer with slew-rate compensation. The threshold voltage¡]Vth¡^ of PMOSs and NMOSs varying with process variation could be detected, respectively. In addition, the voltage and temperature variations could be monitored, respectively, by detecting different charging and discharging times of delay buffers at each PVT corner. By adjusting output currents, the slew rate of output signals could be compensated over 24¢H. Moreover, the maximum data rate with compensation is 133 MHz in contrast with 100 MHz without compensation when VDDIO ¡× 1.8 V, in transmitting mode.