This thesis is composed of two parts : a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, and a 2¡ÑVDD output buffer with process and temperature compensation.
In the first topic, a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, which is able to tolerate 3¡ÑVDD using stacking transistors in the output stage, is proposed. These transistors are biased by corresponding voltage levels which are generated by a dynamic gate bias generator and a floating N-well circuit when transmitting or receiving signals. In order to prevent the input stage transistors
from gate-oxide overstress, an NMOS clamping technique is used to block high input voltages. This design can receive and transmit 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5.0 V) signals, which has been implemented using TSMC 1P6M 0.18 £gm CMOS process.
The second topic shows a 2¡ÑVDD output buffer with process and temperature compensation using 1P6M 0.18 £gm CMOS process. In this design, a novel process and temperature variation detector is proposed to detect the corners of NMOS and PMOS, respectively. The driving capability of the output stage is enhanced at those corners with low output currents. By contrast, the driving currents is reduced at those corners with high output currents to reduce the variation of output slew rate.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0701110-173316 |
| Date | 01 July 2010 |
| Creators | Liu, Jen-Wei |
| Contributors | Chua-Chin Wang, Sying-Jyan Wang, Chih-Peng Li, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701110-173316 |
| Rights | not_available, Copyright information available at source archive |
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