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Towards Achieving Highly Parallelized Publish/Subscribe Matching at Line-rates Using Reconfigurable Hardware

We present fpga-ToPSS (Toronto Publish/ Subscribe System), an efficient
FPGA-based middleware platform geared towards high-frequency and low-latency event processing. fpga-ToPSS is built over reconfigurable hardware---FPGAs---to achieve line-rate processing by exploiting
unprecedented degrees of parallelism and potential for pipelining,only available through custom-built, application-specific and low-level logic design.

Furthermore, our middleware solution hosts an event processing engine that is built on a hardware-based packet processor and Boolean
expression matcher. Our middleware vision extends to a wide range of applications including real-time data analytics, intrusion detection, algorithmic trading, targeted advertisement, and (complex) event
processing.

Identiferoai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/31445
Date20 December 2011
CreatorsSingh, Harshvardhan P.
ContributorsJacobsen, Hans-Arno
Source SetsLibrary and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada
Languageen_ca
Detected LanguageEnglish
TypeThesis

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