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A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications.

Identiferoai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:82996
Date20 January 2023
CreatorsZeinolabedin, Seyed Mohammad Ali, Schüffny, Franz Marcus, George, Richard, Kelber, Florian, Bauer, Heiner, Scholze, Stefan, Hänzsche, Stefan, Stolba, Marco, Dixius, Andreas, Ellguth, Georg, Walter, Dennis, Höppner, Sebastian, Mayr, Christian
PublisherIEEE
Source SetsHochschulschriftenserver (HSSS) der SLUB Dresden
LanguageEnglish
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/acceptedVersion, doc-type:article, info:eu-repo/semantics/article, doc-type:Text
Rightsinfo:eu-repo/semantics/openAccess
Relation1940-9990, 10.1109/TBCAS.2022.3142987, info:eu-repo/grantAgreement/European Commission/H2020 | RIA/824162//A Synaptically connected brain-silicon Neural Closed-loop Hybrid system/SYNCH

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