In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC. The original table-based CORDIC can be divided into two stages, coarse stage and fine stage. We also propose the three-stage architectures, composed of traditional pipeline CORDIC, Rom/Multiplier architecture and linear approximation. Detailed analysis and estimation in area and latency of these different two-stage and three-stage architectures with different bit accuracy are given in order to determine the best architecture design for a particular precision. Finally, we choose one of the architectures to implement, compare the results, and show its applications.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0831110-160513 |
| Date | 31 August 2010 |
| Creators | Lee, Cheng-Han |
| Contributors | Tso-Bing Juang, Shen-Fu Hsiao, Chuen-Yau Chen, Shiann-Rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513 |
| Rights | unrestricted, Copyright information available at source archive |
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