This report has been compiled to document the thesis work carried out by Anton Andersson for Coresonic AB. The task was to develop an accelerator that could generate complex numbers suitable for fast fourier transforms (FFT) and tuning the phase of complex signals (NCO). Of many ways to achieve this, the CORDIC algorithm was chosen. It is very well suited since the basic implementation allows rotation of 2D-vectors using only shift and add operations. Error bounds and proof of convergence are derived carefully The accelerator was implemented in VHDL in such a way that all critical parameters were easy to change. Performance measures were extracted by simulating realistic test cases and then compare the output with reference data precomputed with high precision. Hardware costs were estimated by synthesizing a set of different configurations. Utilizing graphs of performance versus cost makes it possible to choose an optimal configuration. Maximum errors were extracted from simulations and seemed rather large for some configurations. The maximum error distribution was then plotted in histograms revealing that the typical error is often much smaller than the largest one. Even after trouble-shooting, the errors still seem to be somewhat larger than what other implementations of CORDIC achieve. However, precision was concluded to be sufficient for targeted applications. / Den här rapporten dokumenterar det examensarbete som utförts av AntonAndersson för Coresonic AB. Uppgiften bestod i att utveckla enaccelerator som kan generera komplexa tal som är lämpliga att använda försnabba fouriertransformer (FFT) och till fasvridning av komplexasignaler (NCO). Det finns en mängd sätt att göra detta men valet föllpå en algoritm kallad CORDIC. Den är mycket lämplig då den kan rotera2D-vektorer godtycklig vinkel med enkla operationer som bitskift ochaddition. Felgränser och konvergens härleds noggrannt. Acceleratorn implementerades i språket VHDL med målet att kritiskaparametrar enkelt skall kunna förändras. Därefter simuleradesmodellen i realistiska testfall och resulteten jämfördes medreferensdata som förberäknats med mycket hög precision. Dessutomsyntetiserades en mängd olika konfigurationer så att prestanda enkeltkan viktas mot kostnad.Ur de koefficienter som erhölls genom simuleringar beräknades detstörsta erhållna felet för en mängd olika konfigurationer. Felenverkade till en början onormalt stora vilket krävde vidareundersökning. Samtliga fel från en konfiguration ritades ihistogramform, vilket visade att det typiska felet oftast varbetydligt mindre än det största. Även efter felsökning verkar acceleratorngenerera tal med något större fel än andra implementationer avCORDIC. Precisionen anses dock vara tillräcklig för avsedda applikationer.

<p>This report has been compiled to document the thesis work carried out by Anton Andersson for Coresonic AB. The task was to develop an accelerator that could generate complex numbers suitable for fast fourier transforms (FFT) and tuning the phase of complex signals (NCO). Of many ways to achieve this, the CORDIC algorithm was chosen. It is very well suited since the basic implementation allows rotation of 2D-vectors using only shift and add operations. Error bounds and proof of convergence are derived carefully The accelerator was implemented in VHDL in such a way that all critical parameters were easy to change. Performance measures were extracted by simulating realistic test cases and then compare the output with reference data precomputed with high precision. Hardware costs were estimated by synthesizing a set of different configurations. Utilizing graphs of performance versus cost makes it possible to choose an optimal configuration. Maximum errors were extracted from simulations and seemed rather large for some configurations. The maximum error distribution was then plotted in histograms revealing that the typical error is often much smaller than the largest one. Even after trouble-shooting, the errors still seem to be somewhat larger than what other implementations of CORDIC achieve. However, precision was concluded to be sufficient for targeted applications.</p> / <p>Den här rapporten dokumenterar det examensarbete som utförts av AntonAndersson för Coresonic AB. Uppgiften bestod i att utveckla enaccelerator som kan generera komplexa tal som är lämpliga att använda försnabba fouriertransformer (FFT) och till fasvridning av komplexasignaler (NCO). Det finns en mängd sätt att göra detta men valet föllpå en algoritm kallad CORDIC. Den är mycket lämplig då den kan rotera2D-vektorer godtycklig vinkel med enkla operationer som bitskift ochaddition. Felgränser och konvergens härleds noggrannt. Acceleratorn implementerades i språket VHDL med målet att kritiskaparametrar enkelt skall kunna förändras. Därefter simuleradesmodellen i realistiska testfall och resulteten jämfördes medreferensdata som förberäknats med mycket hög precision. Dessutomsyntetiserades en mängd olika konfigurationer så att prestanda enkeltkan viktas mot kostnad.Ur de koefficienter som erhölls genom simuleringar beräknades detstörsta erhållna felet för en mängd olika konfigurationer. Felenverkade till en början onormalt stora vilket krävde vidareundersökning. Samtliga fel från en konfiguration ritades ihistogramform, vilket visade att det typiska felet oftast varbetydligt mindre än det största. Även efter felsökning verkar acceleratorngenerera tal med något större fel än andra implementationer avCORDIC. Precisionen anses dock vara tillräcklig för avsedda applikationer.</p>

In addition to the previous pipelined floating-point CORDIC design, three different architectures supporting both CORDIC rotation mode and vectoring mode are proposed in this thesis. Detailed analysis and comparison of these architectures are addressed in order to choose the best architecture with minimized area cost and computation latency given the required bit accuracy. Based on the comparison, we have chosen the best architecture and implemented an IEEE single precision floating-point CORDIC processor. The mathematical analysis of the computation errors is done to minimize the bit width of the composing arithmetic components during implementation. The comparison results of different architectures also serve as a general guideline for the design of floating-point sine/cosine units. Finally, we study the application of the floating-point CORDIC to 3D graphics acceleration.

The current trends of mobile battery-powered devices make area and power critical design constraints in many applications. It is important that embedded software implementations execute any given task as power efficiently as possible. These tasks often require the computation of transcendental functions (sine, cosine, exponential, logarithm, etc.). The CORDIC algorithm can be used to implement an area-efficient hardware accelerator to assist in the computation of many of these functions while reducing the total energy consumed. This report presents the design and implementation of a fixed-point CORDIC rotator. The CORDIC rotator is used to assist in the computation of IEEE-754 single-precision floating-point exponentials. Power simulation results show the CORDIC-assisted exponent computation consumes 81.42% less energy as compared with the unassisted software solution while adding less than 10% to the gate count of the original system. / text

<p>Abstract CORDIC (Coordinate Rotation Digital Computer) is an iterative algorithm for the calculation of a two-dimensional vector in circular, linear or hyperbolic coordinate systems. This paper presents a survey of known CORDIC algorithms and architectures for the rotation and vectoring mode in the circular cordinate system. In addition an implementation of the differential CORDIC algorithm in VHDL has been done. The implementation is designed to keep the fast timing and throughput characteristic known for on-line redundant arithmetic.</p>

Abstract CORDIC (Coordinate Rotation Digital Computer) is an iterative algorithm for the calculation of a two-dimensional vector in circular, linear or hyperbolic coordinate systems. This paper presents a survey of known CORDIC algorithms and architectures for the rotation and vectoring mode in the circular cordinate system. In addition an implementation of the differential CORDIC algorithm in VHDL has been done. The implementation is designed to keep the fast timing and throughput characteristic known for on-line redundant arithmetic.

In this paper, we propose an area-time efficient design for redundant CORDIC-based SIN/COS evaluation by predict on the polarity of micro-rotations using a novel technique called ¡§Base Transfer angle Decomposition Algorithm¡¨(BTDA). The proposed design benefits from a constant scaling and requires no correcting iterations. By predicting the polarity of the signed bit of the micro-rotation, the critical paths of the unfolded and the pipelined designs involve only the X and Y recurrences. The implementations of BTDA architectures for 24-bit wide CORDIC-Base SIN/COS generator were synthesized using FPGA tools (XILINX Foundation Series version 2.1i), and the area-time complexities are presented for unfolded as well as pipelined designs. The proposed design results save more than 25% hardware area with speed-up of more than 30% compared with the exiting methods. Keywords: CORDIC, BTDA, Redundant, SIN/COS, FPGA

Zugl.: Zürich, Techn. Hochsch., Diss., 2009

This thesis proposes an optimized Co-ordinate Rotation Digital Computer (CORDIC) algorithm in the rotation and extended vectoring mode of the circular co-ordinate system. The CORDIC algorithm computes the values of trigonometric functions and their inverses. The proposed algorithm provides the result with a lower overall latency than existing systems. This is done by using redundant representations and approximations of the required direction and angle of each rotation. The algorithm has been designed to provide the result in a fixed number of iterations $n$ for the rotation mode and $3\lceil n/2 \rceil + \lfloor n/2 \rfloor$ for the extended vectoring mode; where, $n$ is a design parameter. In each iteration, the algorithm performs between 0 and $p/n$ parallel rotations, where, $p$ is the number of precision bits and $n$ is the selected number of iterations. A technique to handle the scaling factor compensation for such an algorithm is proposed. The results of the functional verification for different values of $n$ and an estimation of the overall latency are presented. Based on the results, guidelines to choosing a value of $n$ to meet the required performance have also been presented.

In this thesis, the traditional fixed-point CORDIC algorithm is extended to floating-point version in order to calculate transcendental functions (such as sine/cosine, logarithm, powering function, etc.) with high accuracy and large range. Based on different algorithm derivations, two different floating-point high-throughput pipelined CORDIC architectures are proposed. The first architecture adopts barrel shifters to implement the shift operations in each pipelined stage. The second architecture uses pure hardwired method for the shifting operations. Another key contribution of this thesis is to analyze the execution errors in the floating-point CORDIC architectures and make comparison with the execution resulting from pure software programs. Finally, the thesis applies the floating-point CORDIC to realizing the rotation-related operations required in 3D graphics applications.