In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC. The original table-based CORDIC can be divided into two stages, coarse stage and fine stage. We also propose the three-stage architectures, composed of traditional pipeline CORDIC, Rom/Multiplier architecture and linear approximation. Detailed analysis and estimation in area and latency of these different two-stage and three-stage architectures with different bit accuracy are given in order to determine the best architecture design for a particular precision. Finally, we choose one of the architectures to implement, compare the results, and show its applications.

In this thesis, an efficiency method for reducing the rotation ROM size in table-based architecture is proposed. The original rotation can be divided into two stages, coarse stage and fine stage. Our approach modifies the previous two-stage rotation method and proposes a multi-stage architecture and discuses three-stage phase calculation. The effect of table reduction is more apparently for higher accuracy requirement in the three-stage architecture. The total area of the previous two-stage architecture is larger than the proposed table-reduced three-stage architecture because the table size takes a significant ratio of the total area especially when the required bit accuracy is large. In the proposed three-stage design, there are two different types of architectures, depending on the rotation angles in the first and second rotation stages. Comparison of different types of architecture with the previous method shows that our designs indeed reduce the table size and the total area significantly.

Rutiner skrivna i Verilog har utvecklats för avkodning av en frekvensmodulerad signal givet ett Analog Devices AD9874-chip. Olika metoder för I/Q-demodulation har utvärderats och av dessa har CORDIC valts och implementerats i Verilog. Koden har till viss del testats på en IGLOO nano-FPGA men framförallt simulerats och verifierats i ModelSim. / Routines written in Verilog have been developed to perform I/Q-demodulation of a frequency modulated signal given valuesfrom a Analog Devices AD9874 chip. Different methods for I/Q-demodulation have been evaluated and among theseCORDIC has been chosen and implemented in Verilog. The code has to some extent been tested on a IGLOO nano FPGA but foremost been simulated and verified in ModelSim.

Motion and tilt have long hindered the accuracy, reliability, and response of magnetic detection systems. Perturbations in the magnetic field reading resulting from motion cause degradation of the output signal, compromising the performance and reliability of the magnetometer system. The purpose of this document is to describe the development, construction, and testing of a tilt-stabilized three-axis magnetic field sensor. The sensor is implemented as a three-axis general-purpose magnetic field sensor, with the additional capability of being implemented as a compass. Design and construction of system hardware is discussed, along with software development and implementation. Finite impulse response filters are designed and implemented in hardware to filter the acquired magnetic signals. Various designs of median filters are simulated and tested for smoothing inclination signal irregularities and noise. Trigonometric conversions necessary for tilt-compensation are calculated in software using traditional methods, as well as the Coordinate Rotation Digital Computer (CORDIC) algorithm. Both calculation methods are compared for execution time and efficiency. Successful incorporation of all design aspects leads to detection and output of stable earth magnetic fields, sinusoidal signals, and aperiodic signatures while the magnetometer system is subject to significant tilt motion. Optimized system execution time leads to a maximum detectable signal bandwidth of 410 Hz. Integration of azimuth angle calculation is incorporated and is successfully tested with minimal error, allowing the system to be used as a compass. Results of the compensated system tests are compared to non-compensated results to display system performance, including tilt-compensation effectiveness, noise attenuation, and operational speed. / Master of Science

<p>This work is focused on the CORDIC algorithm for wireless LAN. The primary task is to create a VHDL description for CORDIC vector rotation algorithm. </p><p>The basic research has been carried out in MATLAB. The VHDL implementation of the CORDIC algorithm is based on the results obtained from the MATLAB simulation. Mentor Graphics FPGA Advantage© for Xilinx 4010XL FPGA has been used for the hardware implementation.</p>

<p>In this thesis, we explore different algorithms for the inversion of Vandermonde matrices and the corresponding suitable architectures for implement in FPGA. The inversion of Vandermonde matrix is one of the three master projects of the topic, Implementation of a digital error correction algorithm for time-interleaved analog-to-digital converters. The project is divided into two major parts: algorithm comparison and optimization for inversion of Vandermonde matrix; architecture selection for implementation. A CORDIC algorithm for sine and cosine and Newton-Raphson based division are implemented as functional blocks.</p>

This work is focused on the CORDIC algorithm for wireless LAN. The primary task is to create a VHDL description for CORDIC vector rotation algorithm. The basic research has been carried out in MATLAB. The VHDL implementation of the CORDIC algorithm is based on the results obtained from the MATLAB simulation. Mentor Graphics FPGA Advantage© for Xilinx 4010XL FPGA has been used for the hardware implementation.

In this thesis, we explore different algorithms for the inversion of Vandermonde matrices and the corresponding suitable architectures for implement in FPGA. The inversion of Vandermonde matrix is one of the three master projects of the topic, Implementation of a digital error correction algorithm for time-interleaved analog-to-digital converters. The project is divided into two major parts: algorithm comparison and optimization for inversion of Vandermonde matrix; architecture selection for implementation. A CORDIC algorithm for sine and cosine and Newton-Raphson based division are implemented as functional blocks.

Functional evaluation is one of key arithmetic operations in many applications including 3D graphics and stereo. Among various designs of hardware-based function evaluation methods, piecewise polynomial approximation is the most popular approach which interpolates the piecewise function curve in a sub-interval using polynomials with polynomial coefficients of each sub-interval stored in an entry of a lookup table ROM. The conventional piecewise methods usually determine the bit-widths of each ROM entry, multipliers, and adders by analyzing the various error sources, including polynomial approximation errors, coefficient quantization errors, truncation errors of arithmetic operations, and the final rounding error. In this thesis, we present a new piecewise function evaluation design by considering all the error sources together. By combining all the error sources during the approximation, quantization, truncation and rounding, we can efficiently reduce the area cost of ROM and the corresponding arithmetic units in the design of CORDIC processors.

Abstract¡G This thesis mainly implemented an RF transmitter with high efficiency and high linearity. A Cartesian to Polar transformation was implemented by CORDIC algorithm using FPGA. By replacing the envelope detector and limiter in traditional envelope elimination and restoration transmitter, this technique not only achieves more accurate modulation quality, but also becomes more suitable for single chip system. Applying the first order delta-sigma modulation and highly efficient switching-mode DC converter, the envelope signal was amplified highly efficiently. Due to the class-E power amplifier having good linear relation between output voltage and supply voltage, the polar modulation transmitter can achieve high efficiency and high linearity simultaneously. Furthermore, this thesis purposed a new transmitter with two-terminal time-varying modulation. The IQ modulated signal was fed to the input terminal of class-E amplifier, while the envelope signal was used to amplitude modulate the voltage supply terminal. With dynamic input power control, the conversion efficiency and linearity are independent of output power in the purposed architecture. From the experimental results, while transmitting a QPSK-modulated CDMA2000 1x signal with 1.2288 Msps data rate, the transmitter achieve 48 % in drain efficiency, 47 dB in ACPR, and 6 % in EVM at the output power ranging from 10 to 22 dBm.