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Thermal Stress Analysis of Flip Chip in CSP

Abstract
The thesis is aimed to analyze the flip chip in chip scale package (CSP) by finite element method incorporated with software ANSYS due to thermally cyclic loading. The coefficient of thermal expansion (CTE) of underfill and different mechanical properties of four kinds underfill-A, B, C, D and with/without metal cap are considered as parameters. The effects of above-mentioned parameters on package¡¦s displacement, strain and stress fields are studied.
The results show that the maximum equivalent strain and stress take place at the interface between chip and underfill far away from the center of the whole package and on the top of the most outside solder bump in the solder joint. The larger the CTE of underfill is, the larger the maximum equivalent strain and stress are. Package with metal cap can reduce the displacement to almost half or more of that without cap, but increase the values of maximum equivalent strain and stress. No matter with metal cap or not, the underfill D is the best choice. Hence, the underfill material properties possess lower CTE and larger Young¡¦s modulus than those of solder bump.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0718101-235508
Date18 July 2001
CreatorsYeh, Shiao-Chian
ContributorsMing Chen, Ming-Hwa Jen, Chorng-Fuh Liu
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718101-235508
Rightsunrestricted, Copyright information available at source archive

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