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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

FEM-Simulation der thermo-mechanischen Beanspruchung in Flip-Chip-Baugruppen zur Bewertung ihrer Zuverlässigkeit /

Feustel, Frank. January 2002 (has links) (PDF)
Techn. Univ., Diss.--Dresden, 2002.
2

A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Insdustry in Taiwan -Case Study on S Company

Cheng, Kun-chu 29 January 2004 (has links)
A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Industry in Taiwan¡X Case Study on S Company Abstract The success of semiconductor industry in Taiwan significantly lies on the complete demarcation of the industry chain by companies involved in each area of IC design, foundry, packaging and testing. Nonetheless, packaging and testing are generally categorized to one industry as the major company usually runs packaging business in line with testing by emphasizing their turn-key solution. However, this concept will not be applied in the future even followed by the quantum breakthrough on the structure of the industry chain. This is a qualitative descriptive study mainly on analysis of competitive advantage and strategy of Flip Chip Packaging Industry in Taiwan. The theme studied is hardly assessed by quantified data. However through the researcher¡¦s macro review of the industry environment as well as micro review of specific individual case with primary and secondary data all-around collected, the present situation, character and trend of the industry are understood by analyzing external environment and internal corporate, searching source of competitive advantage in line with a case study of competitive strategy. The conclusion on future competitive strategy of Flip Chip Packaging Industry in Taiwan based on the case study is followed: 1. Under the trend of global demarcation with analysis, the future operation mode of Taiwan Flip Chip Packaging Industry should be transformed from low skill level to high technique intensive level through virtual integration of packaging and testing from the back end and IC design of the front end, which results in promoting the integration value of industry chain as well as providing the most efficient producing system to the globe. 2. Reviewing the current trend, development and competitors¡¦ competitive strategy of Taiwan Flip Chip Packaging Industry, analysis shows that under the evolution of technique and product, Taiwan Flip Chip Packaging Industry should take advantage of the special needs from IC design industry and IDM factories to devote to technique integration, application and development in the future. In addition the ability to innovate and establish standard will be uplifted with raising competitive from a complete industry chain and advanced foundry advantage. 3. Researching the core competitive from the case study and presenting the future competitive strategy of Taiwan Flip Chip Packaging Industry shows that differentiation directs the competition in line with stepping into production service and production research and development to replace cost advantage. Key Word: Competitive Advantage, Competitive Strategy, Core Source , Flip Chip Package
3

The Study of Alignment Shift in Flip-Chip Bonding for VCSEL Array

Chen, Cong-Ching 25 June 2001 (has links)
The study of alignment shift in flip chip bonding for VCSEL array was studied experimentally. We calculated the relation between the restoring force and the solder volume by the simulation software PadCAD. The metal pad size were 10£gm, 20£gm, 30£gm in diameter shape and 40£gm in square shape. The solder bump was electroplat by bidirection pulse in the silicon bench which was evaporated by Au/Pt/Ti. The oxidization in the surface of the solder was removed by using flux. The VCSEL array and the Si-bench in flip chip bonding was operated at the temperature 210¢J and 5 seconds. After the flip chip bonding, the minimum alignment shift in X direction was measured to be 2.2£gm. Base on the alignment shift measured result, the maximum coupling efficiency was calculated to be 48% for VCSEL array module.
4

Numerical Simulation on Thermal Fatigue of a Flip Chip Scale Packaging

Chen, Ping-Ju 27 June 2002 (has links)
Abstract The thesis is aimed to simulate the flip chip in chip scale package (FCCSP) by finite element method incorporated with software ANSYS due to thermally cyclic loading. The difference between two-dimensional and tree-dimensional structures is conferred. The position and height of solder bump in FCCSP and cyclic temperature are considered as parameters. The effects of above-mentioned parameters on package¡¦s fatigue models and fatigue damage are studied. The results show that the two-dimensional structure can help us to understand the position of the maximum displacement and the maximum equivalent strain. However, the values of numerical result in the two- dimensional structure are not very accurate. The fatigue fracture will first take place at the top of the most outside solder bump far away from the center of the whole package. If the height of solder bump is lower, the fatigue fracture of solder bump is faster. If the duration time of high and low temperatures is longer, the fatigue fracture due to creep of solder bump becomes faster. When the height of solder bump is change, the change of fatigue damage with plastic strain of solder bump will more obvious than the change of fatigue damage due to creep of solder bump. The extension of duration time of high and low temperatures will increase fatigue damage due to creep of solder bump, but not change the fatigue damage with plastic strain of solder bump. When the height of solder bump is reduced or the duration time of high and low temperatures is extended will increase fatigue damage subjected to cyclic temperature.
5

Thermo-Mechanical Deformation and Stress Analysis of Flip-Chip Ball Grid Array

Guo, Yu-Lun 01 July 2003 (has links)
The thesis investigates the thermo-mechanical deformation and stress of a flip-chip package (FCBGA) via both experiment and simulation. First, Shadow Moiré is used to evaluate the warpage of a package at elevated temperature. Then we adopt the finite element method incorporated with the software ANSYS to simulate the warpage of a package and compare the obtained results with experiment at data. Then, the material properties of underfill, the thickness of die and the substrate are considered as important parameters. Their effects on stress and strain fields of package are studied. In case of FCBGA with and without underfill, we find that FCBGA with underfill can reduce stress concentration and increase warpage of a package in comparion with FCBGA without underfill. As for FCBGA with and without heat slug, it is observed that the warpage of FCBGA with heat slug is smaller than that of FCBGA without heat slug. Both stress and strain in the packages of above two cases are similar. The parametric study about the underfill, we find that smaller modulus and CTEs of underfill can reduce the stress and strain of package. However in the consideration of thicknesses of both die and substrate, it is shown that thinner die can reduce stress and strain of package, but thinner substrate does not. So it is suggested that thicknesses of die are the thinner the better.
6

Flip chip and lid attachment assembly process development

Ding, Fei, Johnson, Robert Wayne, January 2006 (has links) (PDF)
Dissertation (Ph.D.)--Auburn University, 2006. / Abstract. Includes bibliographic references (p.99-110).
7

Elektromagnetische Eigenschaften von Flip-Chip-Übergängen im Millimeterwellenbereich

Jentzsch, Andrea. Unknown Date (has links) (PDF)
Techn. Universiẗat, Diss., 2002--Berlin.
8

Flip Chip Solder Residual Improvement and Process CPK Control Analysis

Huang, Jun-Chin 28 July 2007 (has links)
With the progress of the semiconductor technology, the devices scaling down to submicron range leads to increase I/Os number and very fine pitch IC package type; such as BGA, Flip Chip and CSP type packages. For Flip chip packaging, the solder bumping process act as the role of I/O interconnection instead of conventational wirebonding process. The ball mounted process is defined as the solder ball mounted on the Flip Chip Ball Grad Array (FC-BGA) substrate for solder bumping. In this study, how to improve the strength of ball-shear; residual tin capability and capability of process kit are the main issues to be investigated for the ball mounted process. To analyze the root cause and to implement the corrective action are the important purpose for solving the failures occurred on the ball mounted process. The following technologies included as (1) engineering ststictic methodology; JMP (statistical software) (2) Problem solving methodology (PSM) (3) Optimizing the process window (4) Set up the main parameters to analyse in machinery (5) how to monitor the CPK capability & material properties analysis, are used for these issues. Finally, the ball mounted process has been successfully investigated and results in solving the failure of Flip Chip ball mounted process and surface mounted technology (SMT) process for assembly packaging manufacture completely.
9

In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests

Zhang, Jian, January 2003 (has links) (PDF)
Thesis (Ph. D.)--School of Mechanical Engineering, Georgia Institute of Technology, 2004. Directed by Daniel F. Baldwin. / Vita. Includes bibliographical references (leaves 202-210).
10

Fabrication and assembly of ultra thin flexible active printed circuits

Zhang, Tan, January 2006 (has links) (PDF)
Dissertation (Ph.D.)--Auburn University, 2005. / Vita. Includes bibliographical references (ℓ. 79-83).

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