Embedded systems hold immense potential, but their integration into advanced devices comes with significant costs. Malfunctions in these systems can result inequipment failures, posing serious risks and potential accidents. To ensure theirproper functionality, embedded system components undergo rigorous testing phases,which can be time-consuming, especially for components with numerous connections. Therefore, it is crucial to reduce test time while maintaining high-qualitytesting to detect and address failures early in the development cycle, resulting in improved and safer products. This report delves into various techniques and algorithms aimed at expediting testingprocesses, such as machine learning, risk analysis, test parallelization, and combinatorial testing. It examines the practicality of mathematical models and automatedapproaches in real-world companies through experimentation and implementation.In essence, the report tackles the challenges involved in testing embedded systems,explores different approaches to reduce test time, and presents a suitable model formaintaining test quality. The ultimate goal is to present and implement a methodthat effectively reduces test time while upholding an acceptable level of test quality.The obtained results provide valuable insights for future test groups and researchersseeking to optimize their testing processes and deliver safer products
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:lnu-125332 |
| Date | January 2023 |
| Creators | Mwanje, Sami |
| Publisher | Linnéuniversitetet, Institutionen för datavetenskap och medieteknik (DM) |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
Page generated in 0.003 seconds