This thesis proposes a new approach to the design of reliable VLSI interconnects,
based on predictive failure models embedded in a software tool
for reliability analysis.
A method for predicting the failure rate of complex integrated circuit interconnects
subject to electromigration, is presented. This method is based
on the principle of fracturing an interconnect pattern into a number of statistically
independent conductor segments. Five commonly-occurring segment
types are identified: straight runs, steps resulting from a discontinuity
in the wafer surface, contact windows, vias and bonding pads. The relationship
between median time-to-failure (Mtf) of each segment and physical
dimensions, temperature and current density are determined. This model
includes the effect of time-varying current density. The standard deviation
of lifetime is also determined as a function of dimensions. A· minimum
order statistical method is used to compute the failure rate of the interconnect
system. This method, which is applicable to current densities below
106 AI cm2 , combines mask layout and simulation data from the design data
base with process data to calculate failure rates.
A suite of software tools called Reliant (RELIability Analyzer for iNTerconnects)
which implements the algorithms described above, is presented.
Reliant fractures a conductor pattern into segments and extracts electrical
equivalent circuits for each segment. The equivalent circuits are used
in conjunction with a modified version of the SPICE circuit simulator to
determine the currents in all segments and to compute reliability. An interface
to a data base query system provides the capability to access reliability
data interactively. The performance of Reliant is evaluated, based on two
CMOS standard cell layouts. Test structures for the calibration of the
reliability models are provided.
Reliant is suitable for the analysis of leaf cells containing a few hundred
transistors. For MOS VLSI circuits, an alternative approach based on the
use of an event-driven switch-level simulator is presented. / Thesis (Ph.D.)-University of Natal, Durban, 1988.
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:ukzn/oai:http://researchspace.ukzn.ac.za:10413/6887 |
| Date | January 1988 |
| Creators | Frost, David Frank. |
| Contributors | Poole, K. F. |
| Source Sets | South African National ETD Portal |
| Language | English |
| Detected Language | English |
| Type | Thesis |
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