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The purpose of this study is to develop accuracy enhancement techniques for the Time Domain Reflection/Transmission (TDR/T) measurements including the analysis of the error sources for the Enhanced Accuracy TDR/T (EA-TDR/T). These TDR/T techniques are used for IC and IC package interconnect characterization and equivalent circuit model extraction, which are important for evaluating the overall system performance in today's digital IC design. The frequency domain error correction has been used to get parameters for a Device Under Test (DUT) from time domain measurements. The same technique can be used as an intermediate step for obtaining the EA-TDR/T. Careful choice of the acquisition window and precise alignment of the DUT and calibration standard waveforms are necessary to get the accuracy enhancement for the TDR/T. Improved FFT techniques are used in order to recover the actual spectra of the step-like time domain waveforms acquired with an acquisition window with a finite time length. The EA-TDR/T waveform are recovered from error corrected frequency domain parameters of the DUT by launching an ideal excitation at the DUT and finding the response. The rise time of the ideal excitation can be faster than that of the physical excitation in the measurement system. However, excessive high-frequency noise can enter the system if the rise time of the ideal excitation is chosen to be too high. The resulting EA-TDR/T waveforms show significantly less aberrations than the conventional TDR/T waveforms, hence allow us to extract accurate equivalent circuit model for the DUT, which in our case is IC interconnects. / Graduation date: 1995

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Concurrent error detection (CED) is the detection of errors or faults in a circuit or data path concurrent with normal operation of that circuit. The general approach for CED is to calculate a check symbol for the inputs to the circuit under operation, predict the check symbol that will result for the output of the circuit for those inputs, and compare the predicted check symbol to the one that is actually calculated for the output. If the predicted and actual check symbols are different, an error or fault has been detected. The alternative to this check symbol prediction is to use a second copy of the circuit under operation and compare the results of the two circuits. For some classes of circuits the prediction of the output check symbol can require less circuitry than a second copy of the circuit being tested. Four examples of these types of circuits are examined in this dissertation: Arithmetic Logic Units (ALUs), array multipliers, self-synchronous scrambler-descrambler pairs with their intervening data path, and switch fabrics. Faults in integrated circuits tend to produce unidirectional errors. Unidirectional errors are those in which all of the errors are in the same direction (e.g., 0 to 1 errors) within the block of data covered by a given check symbol. For this reason, codes that are optimized for unidirectional errors are the focus of investigation for most of the applications. In particular, the Bose-Lin codes are examined for those applications where unidirectional errors are expected to be typical. In order to examine the performance of the Bose-Lin codes in one of these applications, it was necessary to determine the theoretical performance for Bose- Lin codes for error rates beyond what had been previously studied. This analysis of Bose-Lin codes with large numbers of "burst" errors also included a further generalization of the codes. / Graduation date: 2002

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Reliability of sub-micron analog circuits is directly related to impact ionization and the subsequent changes in threshold voltage and drain current of n-MOSFET devices. This thesis presents theory of the hot-electron effects on the device characteristics and circuit performance, explores several approaches to improve performance at both the device and circuit level, and finally shows a new composite n-MOSFET device which significantly suppresses substrate current - an indication of hot-electron degradation. By using the composite device in the output gain stage of a CMOS differential amplifier with 1p.m technology, the normalized substrate current of the n-channel device is reduced by eight orders of magnitude for a sloping input waveform. The reduction in device substrate current is achieved at the cost of increased area and reduced frequency response. Replacing conventional n-channel devices with composite n-MOSFETs provides a simple way to improve device and circuit reliability without modification of the device structure and/or fabrication process. / Graduation date: 1993

Facing the constantly increasing reliability challenges under technology scaling, the topics in IC reliability technique have been receiving serious attention during recent years. In this work, based on the understanding of existing physical failure models that have been concentrating on the pre-fab circuits, a set of revised models for major failure mechanisms such as electromigration, hot-carrier, and gate oxide wear-out are created. Besides the modeling of degradation behaviors for circuits in design phase, these models tend to deal with the post-fab device characteristics with the presence of physical defects. In addition, the simulation work has been taken from device level to circuit level hierarchically, presenting the evaluation of circuit level reliability such as degradations of circuit level specs and circuit lifetime prediction. For post-fab ICs under electromigration, the expected circuit lifetime is calculated based on statistical processes and the probability theory. By incorporating all physics-of-failure models and applying circuit level simulation approaches, an IC reliability simulator called ARET (ASIC reliability evaluation tool) has been developed. Besides the reliability evaluation, the reliability hotspot identification function is developed in ARET, which is a key step for conducting IC local design-for-reliability approaches. ARET has been calibrated with a series of stress tests conducted at The Boeing Company. Design-for-reliability (DFR) is a very immature technical area, which has been becoming critical with the continuously shrinking reliability safety margin. A novel concept, local design-for-reliability is proposed in this work. This DFR technique is closely based on reliability simulation and hotspot identification. By redesigning the circuit locally around reliability hotspots, this DFR approach offers the overall reliability improvement with the maintained circuit performance. Various DFR algorithms are developed for different circuit situations. The experiments on designed and benchmark circuits have shown that significant circuit reliability improvements can be obtained without compromising performance by applying these DFR algorithms.