Statistical extrapolation is required to predict extreme loads, associated with a target return period, for offshore wind turbines. In statistical extrapolation, “short-term" distributions of the load random variable(s) conditional on the environment are integrated with the joint probability distribution of environmental random variables (from wind, waves, current etc.) to obtain the so-called “long-term" distribution, from which long-term loads may be obtained for any return period. The accurate prediction of long-term extreme loads for offshore wind turbines, using efficient extrapolation procedures, is our main goal. While loads data, needed for extrapolation, are obtained by simulations in a design scenario, field data can be valuable for understanding the offshore environment and the resulting turbine response. We use limited field data from a 2MW turbine at the Blyth site in the United Kingdom, and study the influence of contrasting environmental (wind) regimes and associated waves at this site on long-term loads, derived using extrapolation. This study also highlights the need for efficient extrapolation procedures and for modeling nonlinear waves at sites with shallow water depths. An important first step in extrapolation is to establish robust short-term distributions of load extremes. Using data from simulations of a 5MW onshore turbine model, we compare empirical short-term load distributions when two alternative models for extremes--global and block maxima--are used. We develop a convergence criterion, based on controlling the uncertainty in rare load fractiles, which serves to assess whether or not an adequate number of simulations has been performed. To establish long-term loads for a 5MW offshore wind turbine, we employ an inverse reliability approach, which is shown to predict reasonably accurate long-term loads, compared to a more expensive direct integration approach. We show that blade pitching control actions can be a major source of response variability, due to which a large number of simulations may be required to obtain stable tails of short-term load distributions, and to predict accurate ultimate loads. We address model uncertainty as it pertains to wave models. We investigate the effect of using irregular nonlinear (second-order) waves, compared to irregular linear waves, on loads for an offshore wind turbine. We incorporate this nonlinear irregular wave model into a procedure for integrated wind-wave-response analysis of offshore wind turbines. We show that computed loads are generally somewhat larger with nonlinear waves and, hence, that modeling nonlinear waves is important is response simulations of offshore wind turbines and prediction of long-term loads. / text

Facing the constantly increasing reliability challenges under technology scaling, the topics in IC reliability technique have been receiving serious attention during recent years. In this work, based on the understanding of existing physical failure models that have been concentrating on the pre-fab circuits, a set of revised models for major failure mechanisms such as electromigration, hot-carrier, and gate oxide wear-out are created. Besides the modeling of degradation behaviors for circuits in design phase, these models tend to deal with the post-fab device characteristics with the presence of physical defects. In addition, the simulation work has been taken from device level to circuit level hierarchically, presenting the evaluation of circuit level reliability such as degradations of circuit level specs and circuit lifetime prediction. For post-fab ICs under electromigration, the expected circuit lifetime is calculated based on statistical processes and the probability theory. By incorporating all physics-of-failure models and applying circuit level simulation approaches, an IC reliability simulator called ARET (ASIC reliability evaluation tool) has been developed. Besides the reliability evaluation, the reliability hotspot identification function is developed in ARET, which is a key step for conducting IC local design-for-reliability approaches. ARET has been calibrated with a series of stress tests conducted at The Boeing Company. Design-for-reliability (DFR) is a very immature technical area, which has been becoming critical with the continuously shrinking reliability safety margin. A novel concept, local design-for-reliability is proposed in this work. This DFR technique is closely based on reliability simulation and hotspot identification. By redesigning the circuit locally around reliability hotspots, this DFR approach offers the overall reliability improvement with the maintained circuit performance. Various DFR algorithms are developed for different circuit situations. The experiments on designed and benchmark circuits have shown that significant circuit reliability improvements can be obtained without compromising performance by applying these DFR algorithms.

Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry. Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of: - Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials) - Highly-scaled local and global interconnects - Beyond Cu interconnect - Novel metallization schemes and advanced dielectrics - Interconnect and device reliability - Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM) - 3D and packaging (monolithic 3D, TSV, EMI) - Novel and emerging interconnects Executive Committee: Sang Hoon Ahn (Samsung Electronics Co., Ltd.) Paul R. Besser (Lam Research) Robert S. Blewer (Blewer Scientific Consultants, LLC) Daniel Edelstein (IBM) John Ekerdt (The University of Texas at Austin) Greg Herdt (Micron) Chris Hobbs (Sematech) Francesca Iacopi (Griffith University) Chia-Hong Jan (Intel Corporation) Rajiv Joshi (IBM) Heinrich Koerner (Infineon Technologies) Mehul Naik (Applied Materials Inc.) Fabrice Nemouchi (CEA LETI MINATEC) Takayuki Ohba (Tokyo Institute of Technology) Noel Russell (TEL Technology Center, America) Stefan E. Schulz (Chemnitz University of Technology) Yosi Shacham-Diamand (Tel-Aviv University) Roey Shaviv (Applied Materials Inc.) Zsolt Tokei (IMEC)

Les travaux de cette thèse portent sur la simulation de la dégradation des paramètres électriques des transistors MOS et bipolaires sous stress statiques et dynamiques. Cette étude a été menée à l’aide d’un outil de simulation de fiabilité développé en interne. Selon la technologie MOS ou bipolaire, les mécanismes étudiés ont été successivement : Hot Carrier Injection, Bias Temperature instability, Mixed Mode et Reverse base emitter bias. L’investigation a été aussi étendue au niveau circuit. Nous nous sommes ainsi intéressés à l’effet de la dégradation des transistors sur la fréquence d’un oscillateur en anneau et les performances RF d’un amplificateur faible bruit. Les circuits ont été soumis à des contraintes DC , AC et RF. La prédictibilité, établie de ces dégradations, a été validée par des essais de vieillissement expérimentaux sur des démonstrateurs encapsulés et montés sur PCB. Les résultats de ces études ont permis de valider la précision du simulateur et la méthode de calcul quasi-statique utilisée pour calculer les dégradations sous stress dynamiques. Ces travaux de recherche ont pour but d’inscrire cette approche prédictive dans un flot de conception de circuits afin d’assurer leur fiabilité. / The work of this thesis focuses on the simulation of the electrical parameters degradation of MOS and bipolar transistors under static and dynamic stresses. This study was conducted using an in-house reliability simulation tool. According to the MOS or bipolar technology, the studied mechanisms were successively: Hot Carrier Injection, Bias Temperature instability, Mixed Mode and Reverse base emitter bias. The investigation was then extended to circuit-level. The effect of transistors degradation on a ring oscillator frequency and the RF performances of a low noise amplifier were investigated. The circuits were subjected to DC, AC and RF constraints. Predictability of these degradations has been validated by experimental aging tests on encapsulated and PCB-mounted demonstrators. The results of these studies proved the accuracy of the simulator and validated the quasi-static calculation method used to predict the degradation under dynamic stress. The goal of this research is to embed this predictive approach into a circuit design flow to ensure its reliability.