As the feature size of integrated circuits goes down to the nanometer scale, transient and permanent reliability issues are becoming a significant concern for circuit designers. Traditionally, the reliability issues were mostly handled at the device level as a device engineering problem. However, the increasing severity of reliability challenges and higher error rates due to transient upsets favor higher-level design for reliability (DFR). In this work, we develop several methods for DFR at the circuit level. A major source of transient errors is the single event upset (SEU). SEUs are caused by high-energy particles present in the cosmic rays or emitted by radioactive contaminants in the chip packaging materials. When these particles hit a N+/P+ depletion region of an MOS transistor, they may generate a temporary logic fault. Depending on where the MOS transistor is located and what state the circuit is at, an SEU may result in a circuit-level error. We analyze SEUs both in combinational logic and memories (SRAM). For combinational logic circuit, we propose FASER, a Fast Analysis tool of Soft ERror susceptibility for cell-based designs. The efficiency of FASER is achieved through its static and vector-less nature. In order to evaluate the impact of SEU on SRAM, a theory for estimating dynamic noise margins is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closedform expression. Among the many permanent failure mechanisms that include time-dependent oxide breakdown (TDDB), electro-migration (EM), hot carrier effect (HCE), and negative bias temperature instability (NBTI), NBTI has recently become important. Therefore, the main focus of our work is NBTI. NBTI occurs when the gate of PMOS is negatively biased. The voltage stress across the gate generates interface traps, which degrade the threshold voltage of PMOS. The degraded PMOS may eventually fail to meet timing requirement and cause functional errors. NBTI becomes severe at elevated temperatures. In this dissertation, we propose a NBTI degradation model that takes into account the temperature variation on the chip and gives the accurate estimation of the degraded threshold voltage. In order to account for the degradation of devices, traditional design methods add guard-bands to ensure that the circuit will function properly during its lifetime. However, the worst-case based guard-bands lead to significant penalty in performance. In this dissertation, we propose an effective macromodel-based reliability tracking and management framework, based on a hybrid network of on-chip sensors, consisting of temperature sensors and ring oscillators. The model is concerned specifically with NBTIinduced transistor aging. The key feature of our work, in contrast to the traditional tracking techniques that rely solely on direct measurement of the increase of threshold voltage or circuit delay, is an explicit macromodel which maps operating temperature to circuit degradation (the increase of circuit delay). The macromodel allows for costeffective tracking of reliability using temperature sensors and is also essential for enabling the control loop of the reliability management system. The developed methods improve the over-conservatism of the device-level, worstcase reliability estimation techniques. As the severity of reliability challenges continue to grow with technology scaling, it will become more important for circuit designers/CAD tools to be equipped with the developed methods. / text

Microelectronic systems such as cell phones, computers, consumer electronics, and implantable medical devices consist of subsystems which in turn consist of other subsystems and components. When such systems are designed, fabricated, assembled, and tested, they need to meet reliability, cost, performance, and other targets for being competitive. The design of reliable electronic packaging systems in a systematic and timely manner requires a consistent and unified method for allocating, predicting, and assessing reliability and for recommending design changes at the component and system level with consideration of both random and wearout failures. Accordingly, this dissertation presents a new unified knowledge modeling method for System Design for Reliability (SDfR) called the Reliability Object Model (ROM) method. The ROM method consistently addresses both reliability allocation and assessment for systems composed of series and parallel subsystems. The effectiveness of the ROM method has been demonstrated for allocating, predicting, and assessing reliability, and the results show that ROM is more effective compared to existing methods, providing richer semantics, unified techniques, and improved SDfR quality. Furthermore, this dissertation develops representative reliability metrics for random and wearout failures, and incorporates such metrics into ROM together with representative algorithms for allocation, assessment, and design change recommendations. Finally, this research implemented the ROM method in a computing framework and demonstrated its applicability using several relevant microelectronic system test cases and prototype SDfR tools.

Facing the constantly increasing reliability challenges under technology scaling, the topics in IC reliability technique have been receiving serious attention during recent years. In this work, based on the understanding of existing physical failure models that have been concentrating on the pre-fab circuits, a set of revised models for major failure mechanisms such as electromigration, hot-carrier, and gate oxide wear-out are created. Besides the modeling of degradation behaviors for circuits in design phase, these models tend to deal with the post-fab device characteristics with the presence of physical defects. In addition, the simulation work has been taken from device level to circuit level hierarchically, presenting the evaluation of circuit level reliability such as degradations of circuit level specs and circuit lifetime prediction. For post-fab ICs under electromigration, the expected circuit lifetime is calculated based on statistical processes and the probability theory. By incorporating all physics-of-failure models and applying circuit level simulation approaches, an IC reliability simulator called ARET (ASIC reliability evaluation tool) has been developed. Besides the reliability evaluation, the reliability hotspot identification function is developed in ARET, which is a key step for conducting IC local design-for-reliability approaches. ARET has been calibrated with a series of stress tests conducted at The Boeing Company. Design-for-reliability (DFR) is a very immature technical area, which has been becoming critical with the continuously shrinking reliability safety margin. A novel concept, local design-for-reliability is proposed in this work. This DFR technique is closely based on reliability simulation and hotspot identification. By redesigning the circuit locally around reliability hotspots, this DFR approach offers the overall reliability improvement with the maintained circuit performance. Various DFR algorithms are developed for different circuit situations. The experiments on designed and benchmark circuits have shown that significant circuit reliability improvements can be obtained without compromising performance by applying these DFR algorithms.

abstract: In the three phases of the engineering design process (conceptual design, embodiment design and detailed design), traditional reliability information is scarce. However, there are different sources of information that provide reliability inputs while designing a new product. This research considered these sources to be further analyzed: reliability information from similar existing products denominated as parents, elicited experts' opinions, initial testing and the customer voice for creating design requirements. These sources were integrated with three novels approaches to produce reliability insights in the engineering design process, all under the Design for Reliability (DFR) philosophy. Firstly, an enhanced parenting process to assess reliability was presented. Using reliability information from parents it was possible to create a failure structure (parent matrix) to be compared against the new product. Then, expert opinions were elicited to provide the effects of the new design changes (parent factor). Combining those two elements resulted in a reliability assessment in early design process. Extending this approach into the conceptual design phase, a methodology was created to obtain a graphical reliability insight of a new product's concept. The approach can be summarized by three sequential steps: functional analysis, cognitive maps and Bayesian networks. These tools integrated the available information, created a graphical representation of the concept and provided quantitative reliability assessments. Lastly, to optimize resources when product testing is viable (e.g., detailed design) a type of accelerated life testing was recommended: the accelerated degradation tests. The potential for robust design engineering for this type of test was exploited. Then, robust design was achieved by setting the design factors at some levels such that the impact of stress factor variation on the degradation rate can be minimized. Finally, to validate the proposed approaches and methods, different case studies were presented. / Dissertation/Thesis / Doctoral Dissertation Industrial Engineering 2014

En approchant leurs limites ultimes, les technologies de silicium sont affectées par divers problèmes qui rendent de plus en plus difficile la poursuite de la miniaturisation technologique. Ces problèmes concernent en particulier la dissipation de puissance, le rendement paramétrique (affecté par la variation des paramètres du processus de fabrication, des tension d'alimentation et de la température), et la fiabilité (affectée par ces mêmes variations ainsi que par l'accélération du vieillissement, les interférences et les soft-errors) Cette thèse concerne le développement et la mise en œuvre des architectures de tolérance aux fautes et d'auto-calibration dédiées, ainsi que la validation de leurs capacités d'atténuer les problèmes mentionnés ci-dessus. / Approaching their ultimate limits, silicon technologies are affected by various problems that make more difficult further miniaturization technology. These problems relate particularly to power dissipation, parametric yield (affected by the variation of process parameters of manufacturing, supply voltage and temperature), and reliability (affected by these changes as well as the accelerated aging, interference and soft-errors). This thesis deals with the development and implementation of fault tolerant architectures and dedicated self-calibration and validation of their ability to mitigate the problems mentioned above.

Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today‟s circuits design. An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point. A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation. Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 µm mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators. iv A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO. A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated.

La conception en vue de la fiabilité (DFR, Design for Reliability) consiste à simuler le vieillissement électrique des composants élémentaires pour évaluer la dégradation d'un circuit complet. C'est dans ce contexte de fiabilité et de simulation de cette dernière, qu'une stratégie de conception en vue de la fiabilité a été développée au cours de ses travaux. Cette stratégie, intégrant une approche « système » de la simulation, s'appuie sur l'ajout de deux étapes intermédiaires dans la phase de conception. La première étape est une étape de construction de modèles comportementaux compacts à l'aide d'une méthodologie basée sur une approche de modélisation multi niveaux (du niveau transistor au niveau circuit) des dégradations d'un circuit. La seconde étape consiste alors l'analyse descendante de la fiabilité de ce circuit, à l'aide de simulations électriques utilisant ses modèles comportementaux dits « dégradables », afin de déterminer les blocs fonctionnels et/ou les composants élémentaires critiques de l'architecture de ce dernier, vis-à-vis d'un mécanisme de défaillance et un profil de mission donnés. Cette analyse descendante permet aussi d'évaluer l'instant de défaillance de ce circuit. Les dispersions statiques, lies au procédé de fabrication utilisé, sur les performances d'un lot de CIs ont aussi été prises en compte afin d'évaluer leur impact sur la dispersion des instants de défaillance des circuits intégrés. Ces méthodes ont été appliquées à deux mécanismes de dégradation : les porteurs chauds et les radiations. / Design for reliability (DFR) consists in assessing the impact of electrical ageing of each elementary component, using electrical simulations, on performance degradations of a full device. According to DFR concept and reliability simulation, theses works present a new DFR strategy. This strategy based on the integration of two intermediate phases in the ICs and SoC design flow. The first phase is a bottom-up ageing behavioural modelling phase of a circuit (from transistor level to circuit level). The second phase is a « top-down reliability analyses » phase of this circuit, performing electrical simulations using its ageing behavioural models, in order to determine critical functional blocks and / or elementary components of its architecture according to a failure mechanism and a given mission profile. Theses analyses also allow determining the failure time of this circuit. Statistical dispersions on ICs performances, due to the used manufacturing process, have been taking into account in order to assess their impact on failure time dispersions of a ICs lot. The method has been applied on two degradation mechanisms: hot carriers and radiations.

Ce projet de thèse se situe dans le cadre de l'étude de la fiabilité prédictive de nouveaux concepts d'assemblages microélectroniques de type « system in package » SiP. L'objectif est de développer une méthodologie de fiabilité prédictive adaptée aux nouveaux concepts d'assemblage qui permet d'optimiser et de prédire les performances dès la phase de conception. Elle est ensuite appliquée sur des projets concrets. Cette méthodologie de fiabilité prédictive fait intervenir des études expérimentales, des simulations thermomécaniques et des analyses statistiques pour traiter les données et évaluer la fiabilité et les risques de défaillance. L'utilisation d'outils de simulation des composants électroniques est bien adaptée pour aider à l'évaluation des zones les plus fragiles, la mise en place des règles de conception et la détermination des paramètres les plus influents avec une réduction du temps de mise en marché d'un produit fiable et une optimisation des performances. Les études réalisées sur le silicium avec deux tests : bille sur anneau et test trois points montrent que le rodage et l'épaisseur ont une influence sur la variation de la contrainte et la déflexion du silicium à la rupture. Avec le test trois points, le déclenchement des fissures est lié à la qualité de sciage et de rodage. Cependant avec le test bille sur anneau, seule la qualité de surface influence le déclenchement des fissures. Le test bille sur anneau est bien adapté pour évaluer la qualité de surface du silicium. Avec les techniques chimiques de réduction de contraintes, comme la gravure humide et plasma, la résistance à la rupture a été considérablement améliorée. Ces tests de rupture sur le silicium ont permis de caractériser la rupture du silicium sous une contrainte de flexion et de compléter les résultats de simulation. Ces travaux démontrent, le besoin et l'utilité du prototypage virtuel des composants électroniques et de l'utilisation d'une méthodologie prédictive dans l'évaluation de la fiabilité en l’appliquant sur des composants réels. / This thesis project is a study of the predictive reliability of new microelectronic package concepts such as "system in package" SiP. The objective is to develop a reliable predictive methodology adapted to the new assembly concepts to optimize and to predict the performance at the design phase. Then, the methodology is applied to concrete projects. This methodology of predictive reliability involves the use of experimental studies, thermomechanical simulations and statistical analysis to process the data and assess the reliability and risks of failure. The use of simulation tools for electronic components is well suited to assist in the evaluation of the most fragile areas, the setting up of design rules and the determination of the most influential parameters with a reduction in the setup time market for a reliable and optimized performance. Studies on silicon strength are conducted with two tests: ball on ring test and on three-point bend test show that the grinding and the thickness influence the variation of the stress and deflection of the silicon at break. With the three points bend test, the onset of crack is linked to defects in sawing and grinding zone. However, with the ball on ring test, only the surface quality influences the initiation of cracks. The ball on ring test is well suited for evaluating the quality of the silicon surface. Chemical techniques of stress release, such as wet etching and plasma etching, improve significantly the strength of silicon samples. These tests on silicon dies are used to characterize the breakdown of silicon under bending test and to complete the simulation results. We have demonstrated in this work, the need and the usefulness of the virtual prototyping of electronic components and the use of a predictive methodology in assessing reliability.

Les travaux de cette thèse portent sur la simulation de la dégradation des paramètres électriques des transistors MOS et bipolaires sous stress statiques et dynamiques. Cette étude a été menée à l’aide d’un outil de simulation de fiabilité développé en interne. Selon la technologie MOS ou bipolaire, les mécanismes étudiés ont été successivement : Hot Carrier Injection, Bias Temperature instability, Mixed Mode et Reverse base emitter bias. L’investigation a été aussi étendue au niveau circuit. Nous nous sommes ainsi intéressés à l’effet de la dégradation des transistors sur la fréquence d’un oscillateur en anneau et les performances RF d’un amplificateur faible bruit. Les circuits ont été soumis à des contraintes DC , AC et RF. La prédictibilité, établie de ces dégradations, a été validée par des essais de vieillissement expérimentaux sur des démonstrateurs encapsulés et montés sur PCB. Les résultats de ces études ont permis de valider la précision du simulateur et la méthode de calcul quasi-statique utilisée pour calculer les dégradations sous stress dynamiques. Ces travaux de recherche ont pour but d’inscrire cette approche prédictive dans un flot de conception de circuits afin d’assurer leur fiabilité. / The work of this thesis focuses on the simulation of the electrical parameters degradation of MOS and bipolar transistors under static and dynamic stresses. This study was conducted using an in-house reliability simulation tool. According to the MOS or bipolar technology, the studied mechanisms were successively: Hot Carrier Injection, Bias Temperature instability, Mixed Mode and Reverse base emitter bias. The investigation was then extended to circuit-level. The effect of transistors degradation on a ring oscillator frequency and the RF performances of a low noise amplifier were investigated. The circuits were subjected to DC, AC and RF constraints. Predictability of these degradations has been validated by experimental aging tests on encapsulated and PCB-mounted demonstrators. The results of these studies proved the accuracy of the simulator and validated the quasi-static calculation method used to predict the degradation under dynamic stress. The goal of this research is to embed this predictive approach into a circuit design flow to ensure its reliability.