Depuis l'invention du transistor dans les années 50, les performances des composants microélectroniques n'ont cessé de progresser, en passant notamment par l'augmentation de leur densité. Malheureusement, la miniaturisation des composants augmente les coûts de fabrication de façon prohibitive. Une solution, permettant d'accroître la densification et les fonctionnalités tout en limitant les coûts, passe par l'empilement des composants microélectroniques. Leurs connexions électriques s'effectuent alors à l'aide d'interconnexions verticales soudées au moyen d'un joint de brasure. Afin d'empêcher leurs ruptures lors des dilatations thermiques, les interconnexions sont protégées au moyen d'un polymère underfill. L'objectif de cette thèse est d'évaluer la faisabilité et la pertinence d'une nouvelle solution de remplissage par polymère, appelée wafer-level underfill (WLUF). L'écoulement de l'underfill durant l'étape d'assemblage des composants est modélisé afin de prédire les paramètres de scellement idéaux, permettant la formation des interconnexions électriques. Puis, l'intégration de nouveaux underfills, possédant des propriétés thermomécaniques différentes, pouvant affecter l'intégrité et le fonctionnement du dispositif, l'étude de la fiabilité du procédé WLUF et, par conséquent, l'évaluation de sa possibilité d'industrialisation est effectuée. / Since the invention of the transistor in the Fifties, performances of microelectronics components did not cease progressing thanks to their density increase. Unfortunately, miniaturization of components increases manufacturing costs in a prohibitory way. A solution, allowing densification and functionalization increase without costs rise, is microelectronics components stack. Their electrical connections are carried out using vertical interconnections welded by means of solder joints. In order to prevent their ruptures during thermal dilatations, interconnections are protected thanks to polymer underfill. The objective of this thesis is to evaluate the feasibility and the relevance of a new solution of polymer filling, called wafer-level underfill (WLUF). Flow of underfill during components assembly step is modeled in order to predict ideal bonding parameters, allowing electrical interconnections formation. Then, integration of new underfills, having different thermomechanical properties, being able to affect device integrity and functioning, the study of WLUF process reliability and, consequently, the evaluation of its industrialization possibility is carried out.

The influence of underfill material properties on the fatigue life of Ball Grid Array (BGA) packages that are subjected to thermal cycling is investigated in this study. A finite element model is created using Ansys by assuming the existence of an infinite array of solder interconnects, cylindrical in shape, surrounded by underfill material. Axial stresses in the interconnects are determined as a temperature loading is applied. The results show that these normal stresses are on the same order of magnitude as the hydrostatic compressive stresses induced in the solder upon underfill curing. Therefore it is concluded that for the range of underfill properties tested, these Mode I cyclic stresses need to be considered in the development of a fracture-based fatigue life model. In addition, a guideline is provided to aide researchers in designing experiments that will replicate loads on fractured specimens that are consistent with those seen in aerospace applications.

Depuis l'invention du transistor dans les années 50, les performances des composants microélectroniques n'ont cessé de progresser, en passant notamment par l'augmentation de leur densité. Malheureusement, la miniaturisation des composants augmente les coûts de fabrication de façon prohibitive. Une solution, permettant d'accroître la densification et les fonctionnalités tout en limitant les coûts, passe par l'empilement des composants microélectroniques. Leurs connexions électriques s'effectuent alors à l'aide d'interconnexions verticales brasées au moyen d'un joint de brasure. Afin d'empêcher leurs ruptures lors des dilatations thermiques, les interconnexions sont protégées au moyen d'un polymère underfill. L'objectif de cette thèse est d'évaluer la faisabilité et la pertinence d'une nouvelle solution de remplissage par polymère, appelée wafer-level underfill (WLUF). L'écoulement de l'underfill durant l'étape d'assemblage des composants est modélisé afin de prédire les paramètres de scellement idéaux, permettant la formation des interconnexions électriques. Puis, l'intégration de nouveaux underfills, possédant des propriétés thermomécaniques différentes, pouvant affecter l'intégrité et le fonctionnement du dispositif, l'étude de la robustesse du procédé WLUF et, par conséquent, l'évaluation de sa possibilité d'industrialisation est effectuée.

This research details the development of a novel process for four commercially available no-flow fluxing underfills for use with flip chip on FR4 substrates. The daisy chain test die was used such that two point resistance measurements could be used to determine the integrity of the solder interconnects post reflow. The impact of the underfill dispensing pattern on underfill void formation is determined in a full factorial dispense DOE that includes two factors: pattern and speed. Evaluation metrics include underfill material voiding and fillet shape. The impact of the placement process is determined in a second full factorial DOE involving three factors at two levels each: dispense pattern, placement force, and dwell time. Metrics include interconnect yield and underfill voiding. The results of these DOEs are used to select an optimal placement process for each material to be used for the remaining reflow experiments. The process developed is a novel approach to no-flow processing; the material is dispensed to the side of the bond site and allowed to flow under the chip after placement by capillary action during the early stages of reflow. This development allows for void free assemblies using no-flow materials. Reflow parameters are investigated using a parametric approach. The following parameters are varied at 2 levels individually off a baseline profile: Peak Temperature, Time > 183 oC, Peak Ramp Rate, Soak Time, and Soak Temperature. A ranking was developed for each material based on the observable metrics: interconnect yield, underfill material voiding, two point resistance, and a grain area fraction term. The results were used to select an optimal assembly process for each material. Test boards were assembled in replicates of 30 according to the optimal process for each material, and AATC -40 to 125 oC thermal cycling test was performed. The MTTF for these assemblies has exceeded 3000 cycles; the void free process successfully avoids premature failure due to solder extrusion into voids. Further process development work has demonstrated that the process is scalable to larger area array die and other edge dispense patterns have also been demonstrated to result in void free assemblies.

Solder bump is used to connect organic substrate with chip to form Flip Chip package. Comparing to wire bond package, the path is reduced so the electrical performance is much better. Due to the environmental concern, eutectic bump is replaced by lead-free bump gradually. Meanwhile, since wafer technology is improved from 55 nm to 40 nm, the material for dielectric layers is also changed so the material for the package need to revised to meet the characteristic of wafer. Now the laser grooving is adopted before blade sawing to accommodate the brittleness of new 40nm wafer. Also, one extra polyimide is added in the wafer fabrication to reinforce the robustness of the circuit. The stress inside the lead-free bump can be reduced by optimizing the temperature of the reflow process and the speed of cooling. Different UBM structure is also reviewed to find out its affect on the strength of bump and low-K circuit so the failure mode of bump can be predicted. The selection of underfill need to be well considered so, the warpage of package can be reduced, the maximum protection of bump and low-K circuit can be achieved, and the process is easier to control. (The four underfills are reviewed) The reliability test is utilized to decide the best bump composition, the structure of UBM, the selection of underfills and the process parameter. By adding the laser grooving in the wafer sawing process, the chance of crack on die low-K layer is reduced during the reliability test. As for the UBM structure, the POU is better than RPI to reduce the crack of die low-K layer. The result is verified on the package with no underfill by Temperature cycle. Last, the matching of SnCu0.7 bump with SAC305 C4 pad has the best result. During the research, the variance of CTE for the core of substrate contributes less warpage of package, comparing to the difference of Tg for underfills. The adhesion of underfills varies and the underfill UA9 has the best result. The flip chip package with underfill UA9 can passes TCB1000. The optimization of UBM structure for lead-free bump is researched and discussed. Composition of the lead-free bump, process parameter, and cost, those factors are also studied.

No-flow underfill materials that cure during the solder reflow process is a relatively new technology. Although there are several advantages in terms of cost, time and processing ease, there are several reliability challenges associated with no-flow underfills. When micron-sized filler particles are introduced in no-flow underfills to enhance the solder bump reliability, such filler particles could prevent the solder bumps making reliable electrical contacts with the substrate pads during solder reflow, and therefore, the assembly yield would be adversely affected. The use of nano-sized filler particles can potentially improve assembly yield while offering the advantages associated with filled underfill materials. The objective of this thesis is to study the thermo-mechanical reliability of nano-filled epoxy underfills (NFU) through experiments and theoretical modeling. In this work, the thermo-mechanical properties of NFUs with 20-nm filler particles have been measured. An innovative residual stress test method has been developed to measure the interfacial fracture toughness. Using the developed residual stress method and the single-leg bending test, the mode-mixity-dependent fracture toughness for NFU-SiN interface has been determined. In addition to such monotonic interfacial fracture characterization, the interface crack propagation under thermo-mechanical fatigue loading has been experimentally characterized, and a model for fatigue interface crack propagation has been developed. A test vehicle comprising of several flip chips was assembled using the NFU material and the reliability of the flip-chip assemblies was assessed under thermal shock cycles between -40oC and 125oC. The NFU-SiN interfacial delamination propagation and the solder bump reliability were monitored. In parallel, numerical models were developed to study the interfacial delamination propagation in the flip chip assembly using conventional interfacial fracture mechanics as well as cohesive zone modeling. Predictions for interfacial delamination propagation using the two approaches have been compared. Based on the theoretical models and the experimental data, guidelines for design of NFUs against interfacial delamination have been developed.

Depuis l'invention du transistor dans les années 50, les performances des composants microélectroniques n'ont cessé de progresser, en passant notamment par l'augmentation de leur densité. Malheureusement, la miniaturisation des composants augmente les coûts de fabrication de façon prohibitive. Une solution, permettant d'accroître la densification et les fonctionnalités tout en limitant les coûts, passe par l'empilement des composants microélectroniques. Leurs connexions électriques s'effectuent alors à l'aide d'interconnexions verticales soudées au moyen d'un joint de brasure. Afin d'empêcher leurs ruptures lors des dilatations thermiques, les interconnexions sont protégées au moyen d'un polymère underfill. L'objectif de cette thèse est d'évaluer la faisabilité et la pertinence d'une nouvelle solution de remplissage par polymère, appelée wafer-level underfill (WLUF). L'écoulement de l'underfill durant l'étape d'assemblage des composants est modélisé afin de prédire les paramètres de scellement idéaux, permettant la formation des interconnexions électriques. Puis, l'intégration de nouveaux underfills, possédant des propriétés thermomécaniques différentes, pouvant affecter l'intégrité et le fonctionnement du dispositif, l'étude de la fiabilité du procédé WLUF et, par conséquent, l'évaluation de sa possibilité d'industrialisation est effectuée.

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

La tendance actuelle vers l’encapsulation d’un assemblage comportant plusieurs puces favorise l’incorporation d’un procédé de réusinage compatible avec l’enlèvement et le remplacement d’une puce défectueuse. La vérification électrique est un procédé inhérent au réusinage qui identifie facilement les puces défectueuses sans en compromettre leur intégrité. Malheureusement, l’aspect qui optimise l’intégrité mécanique et électrique des dispositifs, soit l’encapsulant (underfill), rend les étapes subséquentes d’enlèvement des puces extrêmement difficile. Il devient alors souhaitable d’évaluer le comportement de certaines puces sans underfill qui sont sujettes aux conditions de vérifications électriques souhaitées afin de déterminer s’il existe une zone de test favorable à la qualité et la fiabilité du produit. Ceci est d’autant plus vrai en considérant le peu de données publiées concernant un chargement en compression qu’une puce sans underfill et sans capot peut supporter. Ce projet de recherche présente une étude du comportement des puces renversées sans capot, utilisant un alliage SAC, qui est sans plomb, pour les interconnexions, face à une charge compressive appliquée directement. Les puces sont assemblées sur un substrat organique sans underfill dans une configuration à plusieurs puces. Pour différentes tailles de puces, une série de compressions ont été observées afin de couvrir une vaste étendue de forces potentiellement utilisées pour assurer le contact électrique du laminé non planaire. Les chargements ont été faits à température ambiante et élevée ainsi qu’à angle normal et incliné. La caractérisation par l’analyse des courbes de chargement, la coplanarité, la mesure des hauteurs des interconnections et la tomographie par rayon X a démontré qu’un angle normal ne provoquait qu’une légère déformation qui était relativement indépendante de la température ou de la force dans l’étendu testé. Bien que les données de fluage semblent entrer dans le cadre des modèles précédemment publiés et un nouveau modèle plus juste a été créé avec l’aide de test de nanoindentation. L’inclinaison du chargement a démontré produire des déformations significatives qui, durant un test électrique typique de 20 minutes, étaient similaire pour un faible ou un grand chargement. Par contre, ces déformations avaient tendance à être plus importantes pour une température élevée et pour une petite taille de puce. De telles déformations ont démontrés induire une recristallisation des grains en une taille plus fine sans retrouver leur forme après un recuit. De plus, les déformations sévères ont démontrées une présence de fissurations à température ambiante et d’espace réduit à température élevée pouvant nuire à l’intégrité de l’assemblage. Un cyclage thermique de 1000 cycles n’a pas induit de défaillance électrique pour le nombre d’échantillons testés, mais des tests avec un plus grand échantillonnage sont recommandés. En somme, cette étude conclue qu’une vérification électrique dans des conditions normales d’une puce sans capot ne va pas endommager l’intégrité des interconnections sans plomb. Toutefois, un contrôle des procédés robustes est nécessaire afin d’éviter des conditions anormales résultant en une inclinaison de la charge qui pourrait compromettre l’intégrité des assemblages.