The recent developments of high resolution flat panel imagers have prompted interests in fabricating smaller on-pixel transistors to obtain higher fill factor and faster speed. This thesis presents fabrication and modeling of short channel amorphous silicon (a-Si:H) vertical thin film transistors (VTFT). <br /><br /> A variety of a-Si:H VTFTs with different channel lengths, from 100 nm to 1 μm, are successfully fabricated using the discussed processing steps. Different structural and electrical characteristics of the fabricated device are measured. The results of I-V and C-V characteristics are comprehensively discussed. The 100 nm channel length transistor performance is diverged from regular long channel TFT characteristics, as the short channel effects become dominant in the device, giving rise to necessity of having a physical model to explain such effects. <br /><br /> An above threshold model for a-Si:H VTFT current characteristics is extracted. The transport mechanisms are explained and simulated for amorphous silicon material to be used in the device model. The final model shows good agreement with experimental results. However, we used numerical simulation, run in Medici, to further verify the model validity. Simulation allows us to vary different device and material parameters in order to optimize fabrication process for VTFT. The capacitance behavior of the device is extensively studied alongside with a TFT breakdown discussion.
| Identifer | oai:union.ndltd.org:WATERLOO/oai:uwspace.uwaterloo.ca:10012/928 |
| Date | January 2005 |
| Creators | Fathololoumi, Saeed |
| Publisher | University of Waterloo |
| Source Sets | University of Waterloo Electronic Theses Repository |
| Language | English |
| Detected Language | English |
| Type | Thesis or Dissertation |
| Format | application/pdf, 1082105 bytes, application/pdf |
| Rights | Copyright: 2005, Fathololoumi, Saeed. All rights reserved. |
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