A true time delay multi-bit MEMS phase shifter topology based on impedance-matched slow-wave CPW sections on a 500µm thick quartz substrate is presented. Design equations based on the approximate model for a distributed line is derived and used in optimization of the unit cell parameters. A semi-lumped model for the unit cell is derived and its equivalent circuit parameters are extracted from measurement and EM simulation data. This unit cell model can be cascaded to accurately predict N-section phase shifter performance. Experimental data for a 4.6mm long 4-bit device shows a maximum phase error of 5.5° and S11 less than -21dB from 1-50GHz. A reconfigurable MEMS transmission line based on cascaded capacitors and slow-wave sections has been developed to provide independent Zo - and β-tuning. In the Zo-mode of operation, a 7.4mm long line provides Zo-tuning from 52 to 40Ω (+/-2Ω) with constant phase between the states through 50GHz. The same transmission line is reconfigured by addressing the MEM elements differently and experimental data for a 1-bit version shows 358°/dB (or 58°/mm) with S11 less than -25dB at 50GHz. The combined effect of Zo- and β-tuning is also realized using a 5-bit version.
An electronically tunable TRL calibration set that utilizes a 4-bit true time delay MEMS phase shifter topology, is demonstrated. The accuracy of the tunable TRL is close to a conventional multi-line TRL calibration and shows a maximum error bound of 0.12 at 40GHz. The Tunable TRL method provides for an efficient usage of wafer area while retaining the accuracy associated with the TRL technique, and reduces the number of probe placements.
| Identifer | oai:union.ndltd.org:USF/oai:scholarcommons.usf.edu:etd-1733 |
| Date | 25 March 2005 |
| Creators | Lakshminarayanan, Balaji |
| Publisher | Scholar Commons |
| Source Sets | University of South Flordia |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Graduate Theses and Dissertations |
| Rights | default |
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