Microprocessor architecture has changed significantly since Intel Corporation developed the first commercial computer chip in the 1970s. The modern processors are much smaller and more powerful than their predecessors. Yet, in the mobile computing era the market demands for smaller, faster, cooler, and more power-efficient CPUs that could provide greater performance-per-watt results.
In this dissertation, we address some of the shortcomings in conventional microprocessor designs and discuss possible means of alleviating them. First, we investigate the energy dissipation in Branch Target Buffer (BTB), a commonly present component in branch prediction unit. Our primary contribution is a speculative allocation technique to improve BTB energy consumption. In this technique, a new on-chip structure predicts the BTB activity and dynamically eliminates unnecessary accesses.
Next, we formulate a quantitative metric to analyze the trade-off between processor energy efficiency and cache energy consumption. We investigate the upper
bound energy and latency budget available for alternative data and instruction cache enhancements.
This dissertation concludes with a novel approach to increase processors’ performance by reducing data cache miss rate. We employ a speculative technique to bridge the performance gap between the common Least Recently Used (LRU) replacement algorithm and the optimal replacement policy. We evaluate the non-optimal decisions made by the LRU algorithm and provide a taxonomy of mistakes, which will aid to identify and avoid similar decisions in future incidents.
| Identifer | oai:union.ndltd.org:uvic.ca/oai:dspace.library.uvic.ca:1828/1372 |
| Date | 28 April 2009 |
| Creators | Jokar Deris, Kaveh |
| Contributors | Baniasadi, Amirali |
| Source Sets | University of Victoria |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Rights | Available to the World Wide Web |
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