This thesis is a part of a bigger project which goal is to make a DSP that is instruction compatible with the Motorola DSP56002. The goal of this part is to make a behavioural model with timing of the address generation unit in the DSP. The AGU unit can handle 4 different types of arithmetic’s including linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles several ways of calculating addresses as post/pre increment/decrement by a number. It can address 3 different memories, where 2 new addresses can be calculated at the same time in different memories. This model will be used as a golden model for the RTL model of the AGU that is one of the main parts in the DSP.
Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-2106 |
Date | January 2003 |
Creators | Gustafsson, Henrik |
Publisher | Linköpings universitet, Institutionen för systemteknik, Institutionen för systemteknik |
Source Sets | DiVA Archive at Upsalla University |
Language | English |
Detected Language | English |
Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
Format | application/pdf |
Rights | info:eu-repo/semantics/openAccess |
Relation | LiTH-ISY-Ex, ; 0271 |
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