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A BIST Architecture for Testing LUTs in a Virtex-4 FPGA

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:toledo1375316199
Date January 2013
CreatorsGadde, Priyanka
PublisherUniversity of Toledo / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199
Rightsunrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

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