A system for extracellular neural interfacing that had the capability for stimulation and recording at multiple electrodes was presented. As the core of this system was a custom integrated circuit (IC) that contained low-noise amplifiers, stimulation buffers, and artifact-elimination circuitry. The artifact-elimination circuitry was necessary to prevent the activity of the stimulation buffers from interfering with the normal functioning of the low-noise amplifiers.
The integrated circuits were fabricated in in a 0.35 micron CMOS process. We measured input-referred noise levels for the amplifiers as low as 3.50 microvolts (rms) in the in the bandwidth 30 Hz-3 kHz, corresponding to the frequency range of neural action potentials. The power consumption was 120 microwatts, corresponding to a noise-efficiency factor of 14.5. It was possible to resume recording signals within 2 ms of a stimulation, using the same electrode for both stimulation and recording.
A filtering algorithm to remove the post-discharge artifact was also presented. The filtering was implemented using a field-programmable gate array (FPGA). The filtering algorithm itself consisted of blanking for the duration of the stimulation and artifact-elimination, followed by a wavelet de-noising. The wavelet de-noising split the signal into frequency ranges, discarded those ranges that did not correspond to neural signals, applied a threshold to the retained signals, and recombined the different frequency ranges into a single signal. The combination of the filtering with the artifact-elimination IC resulted in the capability for artifact-free recordings.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/16192 |
| Date | 06 July 2007 |
| Creators | Blum, Richard Alan |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Dissertation |
Page generated in 0.0021 seconds