In this thesis, we discuss the implementation of a low latency decoding algorithm
for turbo codes and repeat accumulate codes and compare the implementation results
in terms of maximum available clock speed, resource consumption, error correction
performance, and the data (information bit) rate. In order to decrease the latency a
parallelized decoder structure is introduced for these mentioned codes and the results
are obtained by implementing the decoders on a field programmable gate array. The
memory collision problem is avoided by using collision-free interleavers. Through
a proposed quantization scheme and normalization approximations, computational
issues are handled for overcoming the overflow and underflow issues in a fixed point
arithmetic. Also, the effect of different implementation styles are observed.
| Identifer | oai:union.ndltd.org:METU/oai:etd.lib.metu.edu.tr:http://etd.lib.metu.edu.tr/upload/2/12610998/index.pdf |
| Date | 01 September 2009 |
| Creators | Erdin, Enes |
| Contributors | Yilmaz, Ali Ozgur |
| Publisher | METU |
| Source Sets | Middle East Technical Univ. |
| Language | English |
| Detected Language | English |
| Type | M.S. Thesis |
| Format | text/pdf |
| Rights | To liberate the content for METU campus |
Page generated in 0.0016 seconds