The digital product increases widely and vastly. Because we live in the analog world, we require a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed and low power analog to digital converter.
In this thesis, the circuits are designing with TSMC.18 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0807107-102239 |
| Date | 07 August 2007 |
| Creators | Chen, Bo-Hua |
| Contributors | Chia-Hsiung Kao, Ko-Chi Kuo, Shiann-Rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807107-102239 |
| Rights | not_available, Copyright information available at source archive |
Page generated in 0.0022 seconds