With the increased demand for complex digital signal processing systems,
real-time signal processing requires higher throughput systems. In the past, the
throughput has been increased by increasing the clock rates, but
synchronization can become increasingly more difficult. Recently there has
been renewed interest in designing asynchronous digital systems. In an
asynchronous system, there is no global clock, and all modules communicate
through handshaking. In this thesis we demonstrate an implementation of an
FIR filter using asynchronous digital circuit techniques. These asynchronous
design techniques are used to test whether a practical signal processing filter
can be implemented with asynchronous logic. A third-order four-bit filter is
developed and simulated with SPICE, comparing favorably with other available
technologies in speed and power consumption. Although in practice 8-16 bits
are needed, this work is sufficient to demonstrate the feasibility of asynchronous
circuits for filtering applications. A chip is laid out in 2 micron CMOS, and
testing shows that it has a speed-power product comparable with asynchronous
designs fabricated by others. / Graduation date: 1994
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/35774 |
| Date | 08 February 1994 |
| Creators | Oren, Joel A. |
| Contributors | Kiaei, Sayfe |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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