In many digital signal processing applications, we often need some special function units that can compute complicated arithmetic functions such as reciprocal, square-root, base-2 logarithm, power of 2, trigonometric functions, etc. The most popular design approaches to compute these single-value functions are based on look-up tables (LUT) with interpolation. In general, there are two different types of LUT-based method: piecewise and multipartite. As the required bit accuracy increases, the size of LUT increases exponentially. In this thesis, we will develop a generator that can automatically synthesize suitable hardware to compute these special arithmetic functions given the required bit accuracy. In particular, higher-order piecewise method will be supported to reduce the table size for high-accuracy applications. The synthesized arithmetic units are used in the design of a vertex shader for 3D graphics application.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0910108-124935 |
| Date | 10 September 2008 |
| Creators | Lin, Ching-Pin |
| Contributors | Shiann-Rong Kuang, Chuen-Yau Chen, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910108-124935 |
| Rights | not_available, Copyright information available at source archive |
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