As the complexity of System-on-a-Chip (SoC) designs increases, embedded memory components gradually occupy a significant portion of the total area cost, and the reusable memory Intellectual Property (IP) design becomes a critical issue. In this thesis, an automatic cache generator is developed which can be easily integrated into the current cell-based design flow. The generated cache contains both hard IP and soft IP. The storage array circuits are implemented as hard IP to reduce the area cost. The cache control unit is realized as soft IP. The hard IP of the core memory circuits mainly store data and tag information. The implementations of tag arrays can be divided into two categories: RAM-tag design and CAM (Content Addressable Memory)-tag design. We adopt the CAM-tag style in our cache design because CAM cells have the functions of storage as well as data-matching, and thus can be easily used to realize the tag function in cache. The soft IP of cache controller implements the different writing strategies and block replacement methods. The input parameters of the cache generator include cache size, block size, information on set-associativity, writing strategy, replacement methods, etc. The output of the cache generator contains the RTL code for the soft IP and other necessary Models for the hard IP so that the generated cache can be mixed with other pure cell-based design modules during synthesis and placement-and-routing.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0726105-201604 |
| Date | 26 July 2005 |
| Creators | Lin, Shih-Yun |
| Contributors | Chua-Chin Wang, Ming-Der Shieh, Shen-Fu Hsiao, Yun-Zan Chang, Ing-Jer Huang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726105-201604 |
| Rights | not_available, Copyright information available at source archive |
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