An Abstract of the Thesis Adders are the core components in this present multimedia world. Data paths for media signal processing are built using adders and multipliers which can be reconfigured and used based on their word lengths. Reconfigurable adders have significant importance, because of increasing demand in multimedia devices such as cell phones, gaming consoles, music players etc. Our design is capable of processing data with variable word lengths without using any extra circuitry, the design is synthesis of 64 bit energy efficient reconfigurable adder which can perform one 64 bit, two 32 bit, four 16 bit and four 8 bit additions at a time. Our design uses carry skip adders so as to make the over all circuit work faster with less energy. In spite of having many faster adders such as carry propagation adder, carry look ahead adder, carry select adder and others, we choose carry skip adder because it uses less area and considerably less delay and energy. Our circuit has been designed as schematic in Xilinx and simulated using Modelsim synthesizer and was downloaded on an FPGA prototype board XSA Board V1.2. The power of the circuit is calculated using Xpower and delay, energy and energy delay product are compared with the Ripple carry adder. Table 1: Comparison table E=Energy(nJ) D=Delay(ns) E.D(nJ.ns) Ripple carry adder 12.16 155.92 1895.98 Designed adder 8.54 104.2 889.86 In this brief, the designed energy efficient reconfigurable adder is for multimedia designs minimizes the energy delay product, energy consumption, and delay considerably by using carry skip adder.
| Identifer | oai:union.ndltd.org:siu.edu/oai:opensiuc.lib.siu.edu:theses-1456 |
| Date | 01 January 2009 |
| Creators | Dara, chandra babu |
| Publisher | OpenSIUC |
| Source Sets | Southern Illinois University Carbondale |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Theses |
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