Semiconductor scaling has been largely driven by advancements in lithographic technologies. However, the lack of a viable next generation lithography solution since the 180nm node has driven the industry to printing sub-wavelength features. This has led to rising manufacturing costs and diminishing chip yield. In traditional methodologies, manufacturing and design are relatively insulated, with a layout being the only means of communicating design intent to the foundry. In this dissertation, we describe several techniques which utilize electrical information to improve properties of manufactured structures. We aim to show that a bi-directional flow of information between design and manufacturing is key to increasing chip yield. In particular, we target the mask data preparation flow of lithography. We develop an electrically-driven optical proximity correction (ED-OPC) tool that performs electrical matching as opposed to geometric matching in order to achieve lower post-lithography delay error. We then demonstrate how to harness ED-OPC to compensate electrical variability arising from non-lithographic sources as well. We then describe a technique to manufacture circuits with less timing violations across the process window by using design-aware shape tolerances generated from timing information. Finally, we observe that local wiring has low impact on design properties and use this information to modify target wire shapes themselves in order to improve their manufacturability in the presence of process variations. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/ETD-UT-2010-05-1229 |
| Date | 08 October 2010 |
| Creators | Banerjee, Shayak |
| Source Sets | University of Texas |
| Language | English |
| Detected Language | English |
| Type | thesis |
| Format | application/pdf |
Page generated in 0.0022 seconds