Low-swing on-chip interconnect circuits have been viewed as alternative solutions to the problem of delay and power increase of on-chip interconnects. This thesis aims to characterize and optimize several basic low-swing interconnect circuits, by developing simple delay and power estimation methodologies. Accuracies of the proposed methods are validated against SPICE-based simulations on the 90nm technology node. Based on the delay and power estimation methods developed, optimum power-delay trade-off curves are obtained and directly used for comparison among different interconnect circuit strategies. Three low-swing techniques are included, i.e. conventional level converter (CLC), pseudodifferential interconnect circuit (PDIFF), and current-mode signaling (CM). These techniques represent significantly different driver and receiver topologies, where CLC uses lower supply voltage of a normal inverter driver, PDIFF uses NMOS only drivers, while CM has a low impedance termination at the receiving end. In addition, an optimized full-swing repeater-based technique is included as a baseline for comparison. A simplified repeater performance estimation technique considering ramp input signals is also proposed. The most important step in estimating delay of different driver circuits is the accurate estimation of transistor effective resistance, which considers velocity saturation effects and voltage transition patterns. Optimization for the CM circuit for on-chip interconnects requires completely different treatment than the voltage-mode circuits, due to the different and more complex effective driver resistance and termination resistance modeling. Sizing the driver and receiver transistors should be done simultaneously as their resistive values which affect its performance are dependent on each other. Optimum transistor sizing is very dependenton the required voltage swing chosen. Results of our comparisons show that optimized CLC (reduced voltage supply) repeaters appears to give the best general performance with a slight delay overhead compared to full-swing repeaters. The fact that CLC with repeaters has shorter delay than single-segment CM and PDIFF highlights the effectiveness of repeater structures in long wires. The inclusion of inductance and closed-form solutions to derive optimum transistor sizings for various low-swing interconnect circuits may be developed as a future work using delay and power estimation models presented in this thesis, which is a challenging task to do considering the non-linear equations involved.
| Identifer | oai:union.ndltd.org:ADTP/230272 |
| Date | January 2008 |
| Creators | Irfansyah, Astria Nur, Electrical Engineering & Telecommunications, Faculty of Engineering, UNSW |
| Publisher | Awarded by:University of New South Wales. |
| Source Sets | Australiasian Digital Theses Program |
| Language | English |
| Detected Language | English |
| Rights | Copyright Astria Nur Irfansyah, http://unsworks.unsw.edu.au/copyright |
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