Low intrinsic transistor gain in nanometer CMOS technologies imposes implementation difficulties of switched-capacitor (SC) circuits based on a conventional OTA used in delta-sigma ADCs. Zero-crossing-based circuits (ZCBCs) have been proposed as replacements for conventional OTAs in SC circuits, but the efficiency of existing ZCBC-based delta-sigma ADCs trails that of state-of-art conventional delta-sigma ADCs.
The dynamic comparator-based OTA (DCBOTA) is a novel circuit block that performs an equivalent operation of a conventional OTA in a SC circuit by repeatedly detecting the input (Vg) sign and applying output current pulses to move Vg toward zero. The current pulse amplitude, set to the maximum at the beginning of a charge transfer phase, is decremented each time Vg crosses zero. Once Vg crosses zero at the minimum current pulse amplitude, the operation above ceases.
The discrete-time nature of Vg comparison and current pulse injection in the DCBOTA allows use of a dynamic regenerative comparator, which is fast and scaling friendly, instead of the slow scaling-unfriendly open-loop zero-crossing detector used in ZCBCs.
A small final Vg step size is required for high settling accuracy, but it can result in a long settling time. Analysis reveals that the DCBOTA settling time is minimized with a current pulse scaling factor of 3.59 for any final Vg step size.
The comparator and switch noise affects the settling DCBOTA settling accuracy. The relationship between the minimum Vg step size, comparator noise, and switch noise for a given input-referred noise is shown.
The DCBOTA consists of a dynamic regenerative comparator, control logic, and current pulse driver. The comparator evaluates the Vg sign when enabled by the control logic. The control logic enables and resets the comparator, and controls the current pulse amplitude. The current pulse driver applies either a positive or negative output current pulse when triggered by the comparator output.
A 1-1-1-1 MASH delta-sigma ADC using DCBOTAs fabricated in a 65-nm CMOS technology achieved 70.4 dB of peak SNDR over a 2.5-MHz bandwidth dissipating 3.89 mW of power from a 1.2-V supply. Measurements show linear ADC power scaling over sampling frequencies provided by the dynamic operation of the DCBOTAs.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/34974 |
| Date | 08 January 2013 |
| Creators | Yamamoto, Kentaro |
| Contributors | Anthony, Chan Carusone |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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