In this thesis, the design of a scaling-friendly continuous-time closed-loop voltage controlled oscillator (VCO) based Delta-Sigma analog to digital converter (ADC) is introduced. It uses the VCO as both quantizer and integrator, and thus, obviates the need for power-hungry scaling-unfriendly operational transconductance amplifiers (OTAs) and precision comparators. It arranges two VCOs in a pseudo-differential manner, which cancels out even-order distortions. More importantly, it brings an intrinsic clocked averaging (CLA) capability that automatically addresses digital to analog converter (DAC) mismatches. The prototype ADC in 130 nm complementary metal-oxide-semiconductor (CMOS) occupies a small area of 0.03 mm² and achieves 66.5 dB signal to noise and distortion ratio (SNDR) over 2 MHz bandwidth (BW) while sampling at 300 MHz and consuming 1.8 mW under a 1.2 V power supply. It can also operate with a low analog supply of 0.7 V and achieves 65.8 dB SNDR while consuming 1.1 mW. The corresponding figure-of-merits (FOMs) for the two cases are 0.25 pJ/conversion-step and 0.17 pJ/conversion-step, respectively. / text

Low intrinsic transistor gain in nanometer CMOS technologies imposes implementation difficulties of switched-capacitor (SC) circuits based on a conventional OTA used in delta-sigma ADCs. Zero-crossing-based circuits (ZCBCs) have been proposed as replacements for conventional OTAs in SC circuits, but the efficiency of existing ZCBC-based delta-sigma ADCs trails that of state-of-art conventional delta-sigma ADCs. The dynamic comparator-based OTA (DCBOTA) is a novel circuit block that performs an equivalent operation of a conventional OTA in a SC circuit by repeatedly detecting the input (Vg) sign and applying output current pulses to move Vg toward zero. The current pulse amplitude, set to the maximum at the beginning of a charge transfer phase, is decremented each time Vg crosses zero. Once Vg crosses zero at the minimum current pulse amplitude, the operation above ceases. The discrete-time nature of Vg comparison and current pulse injection in the DCBOTA allows use of a dynamic regenerative comparator, which is fast and scaling friendly, instead of the slow scaling-unfriendly open-loop zero-crossing detector used in ZCBCs. A small final Vg step size is required for high settling accuracy, but it can result in a long settling time. Analysis reveals that the DCBOTA settling time is minimized with a current pulse scaling factor of 3.59 for any final Vg step size. The comparator and switch noise affects the settling DCBOTA settling accuracy. The relationship between the minimum Vg step size, comparator noise, and switch noise for a given input-referred noise is shown. The DCBOTA consists of a dynamic regenerative comparator, control logic, and current pulse driver. The comparator evaluates the Vg sign when enabled by the control logic. The control logic enables and resets the comparator, and controls the current pulse amplitude. The current pulse driver applies either a positive or negative output current pulse when triggered by the comparator output. A 1-1-1-1 MASH delta-sigma ADC using DCBOTAs fabricated in a 65-nm CMOS technology achieved 70.4 dB of peak SNDR over a 2.5-MHz bandwidth dissipating 3.89 mW of power from a 1.2-V supply. Measurements show linear ADC power scaling over sampling frequencies provided by the dynamic operation of the DCBOTAs.

Low intrinsic transistor gain in nanometer CMOS technologies imposes implementation difficulties of switched-capacitor (SC) circuits based on a conventional OTA used in delta-sigma ADCs. Zero-crossing-based circuits (ZCBCs) have been proposed as replacements for conventional OTAs in SC circuits, but the efficiency of existing ZCBC-based delta-sigma ADCs trails that of state-of-art conventional delta-sigma ADCs. The dynamic comparator-based OTA (DCBOTA) is a novel circuit block that performs an equivalent operation of a conventional OTA in a SC circuit by repeatedly detecting the input (Vg) sign and applying output current pulses to move Vg toward zero. The current pulse amplitude, set to the maximum at the beginning of a charge transfer phase, is decremented each time Vg crosses zero. Once Vg crosses zero at the minimum current pulse amplitude, the operation above ceases. The discrete-time nature of Vg comparison and current pulse injection in the DCBOTA allows use of a dynamic regenerative comparator, which is fast and scaling friendly, instead of the slow scaling-unfriendly open-loop zero-crossing detector used in ZCBCs. A small final Vg step size is required for high settling accuracy, but it can result in a long settling time. Analysis reveals that the DCBOTA settling time is minimized with a current pulse scaling factor of 3.59 for any final Vg step size. The comparator and switch noise affects the settling DCBOTA settling accuracy. The relationship between the minimum Vg step size, comparator noise, and switch noise for a given input-referred noise is shown. The DCBOTA consists of a dynamic regenerative comparator, control logic, and current pulse driver. The comparator evaluates the Vg sign when enabled by the control logic. The control logic enables and resets the comparator, and controls the current pulse amplitude. The current pulse driver applies either a positive or negative output current pulse when triggered by the comparator output. A 1-1-1-1 MASH delta-sigma ADC using DCBOTAs fabricated in a 65-nm CMOS technology achieved 70.4 dB of peak SNDR over a 2.5-MHz bandwidth dissipating 3.89 mW of power from a 1.2-V supply. Measurements show linear ADC power scaling over sampling frequencies provided by the dynamic operation of the DCBOTAs.

This thesis consists of two topics: A 2.45 GHz ZigBee Receiver Frontend design for home energy-saving systems and a Delta-Sigma ADC with constant-gm amplifier for Battery Management Systems (BMS). A 2.45 GHz ZigBee Receiver Frontend for home energy-saving systems is pre-sented in the first part of this thesis. The proposed ZigBee receiver can be used in areas where wireline solutions are hard to be realized. By employing an LNA at the very frontend of the receiver, the gain is simulated to be 17.376 dB at 2.45 GHz. Besides, by using the double-balanced Gilbert mixer with a current bleeding MOS transistor, the NF and the IIP3 of the mixer are only 5.074 dB and -7.234 dB, respectively. To reduce the phase noise of the receiver, a fractional-N frequency synthesizer with a complementary cross-coupled VCO is adopted. The phase noise of the fractional-N frequency synthe-sizer is 137.7 dBc/Hz. The proposed circuit is carried out and measured on silicon using the standard TSMC 0.18 £gm CMOS process. In the second topic, a Delta-Sigma ADC with constant-gm amplifier is presented. The proposed ADC is particularly designed for the voltage detection circuit in BMS. A constant-gm amplifier is also presented to resolve the nonlinearity of the amplifier de-grading the performance of Delta-Sigma modulator, which is the frontend of the Del-ta-Sigma ADC. With the 4 KHz signal bandwidth, 512 KHz sampling frequency, and 128 oversampling rate, it shows a 85.2 dB SNR, and 12-bit resolution. The backend of the ADC is the decimator, which reduces the sampling frequency compliant with the Nyquist rate rule. The decimator is realized by Verilog code and verified by FPGA. By following the mixed-signal flow, the ADC is realized on a single chip using the standard TSMC 0.25 £gm 60V HV CMOS process.

<p>Many medical, environmental, and industrial control applications rely on wide-dynamic-range sensors and A/D converter systems. For most photo-detector-based applications, the input-current is integrated onto a capacitor, either with a variable time, or a variable capacitor value, followed by a sample-and-hold and a voltage A/D converter. The penalty for achieving wide-dynamic-range with the above approach is power and circuit complexity. </p><p>We propose to use the unique properties of current-input continuous-time Delta-Sigma A/D converters to combine the photo-detector current-integration with simultaneous wide-dynamic-range A/D conversion, using programmable reference currents and programmable clock frequencies. </p><p>A programmable current-input wide-dynamic-range Delta-Sigma A/D converter is designed and fabricated using MOSIS AMI 1.5 um 5 V CMOS process. The programmable A/D converter test results exhibit a consistent 12-bit resolution over the programmability range of the reference-currents, from 17.2 nA to 4.4 uA. The supply-current varies from 60 uA to 240 uA, whereas the A/D converter sample-rates increase from 4 Samples/s to 1 kSamples/s, achieving an overall system-dynamic-range of 20-bits. </p><p>An RF-powered version is designed and fabricated using MOSIS ON 0.5 um 3 V CMOS process. It is designed to work at 128 Samples/s to 11.25 kSamples/s sample-rates, achieving 12-bit resolution with only 128 oversampling ratio. The A/D converter supply-current is designed to range from 10 uA to 70 uA to allow its integration with an RF-power source. The RF-powered version of the programmable Delta-Sigma A/D converter includes an on-chip voltage regulator that generates a stable 3 V DC-voltage, and consumes only 15 uA current.</p> / Dissertation

The rapid development in the semiconductors industry has enabled the placement of multiple chips on a single die. This has helped boost the functionality of modernday application specific integrated circuits (ASICs). Thus, digital circuits are being increasingly placed along-side analog and RF circuits in what are known as mixed signal circuits. As a result, the noise couplings through the substrate now have an increased role in mixed-signal ASIC design. Therefore, there is a need to study the effects of substrate noise and include them in the traditional design methodology. ∆Σ analog-to-digital converters (ADCs) are a perfect example of digital integration in traditionally analog circuits. ADCs, used to interface digital circuits to an analog world, are indispensable in mixed-signal systems and therefore set an interesting case study. A ∆Σ ADC is used in this thesis to study the effects of substrate noise. A background study is presented in the thesis to better understand ∆Σ modulators and substrate couplings. An intensive theoretical background on generation, propagation and reception of substrate noise is presented in light of existing researches. System and behavioural level models are proposed to include the effects of substrate noise in the design stages. A maximum decay of 10dB is seen due to injection of substrate noise system level simulations while a decay of 12dB is seen in behavioural simulations. A solution is proposed using controlled clock tree delays to overcome the effects of substrate noise. The solution is verified on both the system and behavioural levels. The noise models used to drive the studies can further be used in mixed-signal systems to design custom solutions. / Den snabba utvecklingen inom halvledarindustrin har möjliggjort placering av flera marker på en enda dö. Detta har hjälpt till att öka funktionaliteten hos moderna applikationsspecifika integrerade kretsar. Sålunda placeras digitala kretsar i allt högre grad parallella och RF-kretsar i de så kallade blandade signalkretsarna. Som ett resultat har bullerkopplingarna genom substratet nu en ökad roll i ASICdesign med blandad signal. Därför finns det behov av att studera effekterna av substratbuller och inkludera dem i den traditionella designmetoden. ∆Σ analog-till-digital omvandlare är ett perfekt exempel på digital integration i traditionellt analoga kretsar. ADC, som används för att gränssnitta digitala kretsar till en analog värld, är oumbärliga i blandningssignalsystem och är därför en intressant fallstudie. A ∆Σ arkitektur används i denna avhandling för att studera effekterna av substratstörning. En bakgrundsstudie presenteras i avhandlingen för att bättre förstå ∆Σ modulatorer och substratkopplingar. En intensiv teoretisk bakgrund på generering, förökning och mottagande av substratbuller presenteras i ljuset av befintliga undersökningar. Systemoch beteendemodellmodeller föreslås inkludera effekterna av substratbuller i konstruktionsstadiet. Ett maximalt förfall på 10dB ses på grund av injektion av substratbuller på systemnivå medan ett förfall av 12dB ses i beteende simuleringar.En lösning föreslås med hjälp av kontrollerade klockträdfördröjningar för att övervinna effekterna av substratbuller. Lösningen är verifierad på både system och beteendenivåer. De brusmodeller som används för att driva studierna kan vidare användas i blandningssignalsystem för att designa anpassade lösningar.

Continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADC) have emerged as the popular choice to achieve high resolution and large bandwidth due to their low cost, power efficiency, inherent anti-alias filtering and digital post processing capabilities. This work presents a detailed system-level design methodology for a low-power CT ΔΣ ADC. Design considerations and trade-offs at the system-level are presented. A novel technique to reduce the sensitivity of the proposed ADC to clock jitter-induced feedback charge variations by employing a hybrid digital-to-analog converter (DAC) based on switched-capacitor circuits is also presented. The proposed technique provides a clock jitter tolerance of up to 5ps (rms). The system is implemented using a 5th order active-RC loop filter, 9-level quantizer and DAC, achieving 74dB SNDR over 20MHz signal bandwidth, at 400MHz sampling frequency in a 1.2V, 90 nm CMOS technology. A novel technique to improve the linearity of the feedback digital-to-analog converters (DAC) in a target 11-bits resolution, 100MHz bandwidth, 2GHz sampling frequency CT ΔΣ ADC is also presented in this work. DAC linearity is improved by combining dynamic element matching and automatic background calibration to achieve up to 18dB improvement in the SNR. Transistor-level circuit implementation of the proposed technique was done in a 1.8V, 0.18μm BiCMOS process.

No description available.

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling.

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected. / Graduation date: 2010