This thesis includes two topics. The first topic is a 868/915 MHz band ZigBee physical layer design. The second topic is a synchroniza- -tion design of DVB-T demodulators.
The first topic includes simulations and a hardware design. This chip is a physical layer design for IEEE Std 802.15.4 standard applications, including both a transmitter and a receiver for 868/915 MHz band. The measurement of the maximum power is about 144 µW at 2.4 MHz. This chip is proved to be compliant with a low power consumption requirement.
The second topic mainly includes an introduction of the DVZB-T transmitter, equivalent channel model, a demodulation design of the receiver and simulations. The algorithms of the receiver include symbol timing synchronization, frequency offset estimation and its compensation and scattered pilots synchronization.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0704106-155741 |
| Date | 04 July 2006 |
| Creators | Chang, Chih-Yi |
| Contributors | Sying-Jyan Wang, Jih-ching Chiu, Chih-Peng Li, Chua-Chin Wang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0704106-155741 |
| Rights | not_available, Copyright information available at source archive |
Page generated in 0.0013 seconds