An increase in worldwide investments during the past several decades has pro-pelled scienti c breakthroughs in nanoscience and technology research to new and exciting levels. To ensure that these discoveries lead to commercially viable prod-ucts, it is important to address some of the fundamental engineering and scientific challenges related to nanodevices. Due to the centrality of reliability to product integrity, nanoreliability requires critical analysis and understanding to ensure long-term sustainability of nanodevices and systems. In this study, we construct a relia-bility framework for nanoscale dielectric lms used in Metallic Oxide Semiconductor (MOS) devices. The successful fabrication and incorporation of metallic oxides in MOS devices was a major milestone in the electronics industry. However, with the progressive scaling of transistors, the dielectric dimension has progressively decreased to about 2nm. This reduction has had severe reliability implications and challenges including: short channeling e ects and leakage currents due to quantum-mechanical tunneling which leads to increased power dissipation and eventually temperature re-lated gate degradation.
We develop a framework to characterize and model reliability of recently devel-oped gate dielectrics of Si-MOS devices. We accomplish this through the following research steps: (i) the identi cation of the failure mechanisms of Si-based high-k gates (stress, material, environmental), (ii) developing a 3-D failure simulation as a way to acquire simulated failure data, (iii) the identi cation of the dielectric failure prob-ability structure using both kernel estimation and nonparametric Bayesian schemes so as to establish the life pro le of high-k gate dielectric. The goal is to eventually develop the appropriate failure extrapolation model to relate the reliability at the test conditions to the reliability at normal use conditions.
This study provides modeling and analytical clarity regarding the inherent failure characteristics and hence the reliability of metal/high-k gate stacks of Si-based sub-strates. In addition, this research will assist manufacturers to optimally characterize, predict and manage the reliability of metal high-k gate substrates. The proposed reliability framework could be extended to other thin lm devices and eventually to other nanomaterials and devices.
| Identifer | oai:union.ndltd.org:USF/oai:scholarcommons.usf.edu:etd-4694 |
| Date | 31 December 2010 |
| Creators | Otieno, Wilkistar |
| Publisher | Scholar Commons |
| Source Sets | University of South Flordia |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Graduate Theses and Dissertations |
| Rights | default |
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