As the field programmable gate array (FPGA) industry grows device
capacity with Moore's law and expands its market to high performance
computing, scalability of its key CAD algorithms emerges as a new
priority to deliver a user experience competitive to parallel
processors. Among the many walls to overcome, placement stands out due
to its critical impact on both frontend synthesis and backend routing.
To construct a scalable placement flow, we present three innovations
in detailed placement: a legalizer that works well under low
whitespace; a wirelength optimizer based on bipartite matching; and a
cache-aware annealer. When applied to the hundred-thousand cell IBM benchmark
suite, our detailed placer can achieve 27% better wirelength and
8X faster runtime against FastDP, the fastest academic
detailed placer reported, and our full placement flow can achieve 101X faster runtime, with 5% wirelength overhead, against VPR,
the de facto standard in FPGA placements.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/11133 |
| Date | 30 July 2008 |
| Creators | Bian, Huimin |
| Contributors | Zhu, Jianwen |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
| Format | 3663381 bytes, application/pdf |
Page generated in 0.0015 seconds